Lines Matching +full:cortex +full:- +full:a9
1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/zx296702-clock.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
13 enable-method = "zte,zx296702-smp";
16 compatible = "arm,cortex-a9";
18 next-level-cache = <&l2cc>;
23 compatible = "arm,cortex-a9";
25 next-level-cache = <&l2cc>;
32 #address-cells = <1>;
33 #size-cells = <1>;
34 compatible = "simple-bus";
35 interrupt-parent = <&intc>;
38 matrix: bus-matrix@400000 {
39 compatible = "zte,zx-bus-matrix";
43 intc: interrupt-controller@801000 {
44 compatible = "arm,cortex-a9-gic";
45 #interrupt-cells = <3>;
46 #address-cells = <1>;
47 #size-cells = <1>;
48 interrupt-controller;
54 compatible = "arm,cortex-a9-global-timer";
57 interrupt-parent = <&intc>;
61 l2cc: cache-controller@c00000 {
62 compatible = "arm,pl310-cache";
64 cache-unified;
65 cache-level = <2>;
66 arm,data-latency = <1 1 1>;
67 arm,tag-latency = <1 1 1>;
68 arm,double-linefill = <1>;
69 arm,double-linefill-incr = <0>;
73 compatible = "zte,zx296702-pcu";
78 compatible = "zte,zx296702-topcrm-clk";
80 #clock-cells = <1>;
84 compatible = "zte,zx296702-lsp1crpm-clk";
86 #clock-cells = <1>;
90 compatible = "zte,zx296702-lsp0crpm-clk";
92 #clock-cells = <1>;
96 compatible = "zte,zx296702-uart";
104 compatible = "zte,zx296702-uart";
112 compatible = "snps,dw-mshc";
113 #address-cells = <1>;
114 #size-cells = <0>;
117 fifo-depth = <32>;
120 clock-names = "biu", "ciu";
125 compatible = "snps,dw-mshc";
126 #address-cells = <1>;
127 #size-cells = <0>;
130 fifo-depth = <32>;
133 clock-names = "biu", "ciu";