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/Linux-v6.1/arch/arm64/boot/dts/hisilicon/
Dhip05.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/Linux-v6.1/Documentation/devicetree/bindings/arm/
Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
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Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,firestorm-pmu
24 - apple,icestorm-pmu
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Dcpu-capacity.txt6 1 - Introduction
15 2 - CPU capacity definition
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
54 available, final capacities are calculated by directly using capacity-dmips-
58 4 - Examples
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Darm,vexpress-juno.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
37 further subvariants are released of the core tile, even more fine-granular
45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
49 - const: arm,vexpress,v2p-ca9
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/Linux-v6.1/Documentation/devicetree/bindings/cpu/
Dcpu-topology.txt6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
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Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dfsl-ls2080a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
18 compatible = "arm,cortex-a57";
21 cpu-idle-states = <&CPU_PW20>;
22 next-level-cache = <&cluster0_l2>;
23 #cooling-cells = <2>;
28 compatible = "arm,cortex-a57";
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/Linux-v6.1/arch/arm64/boot/dts/amd/
Damd-seattle-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #address-cells = <0x1>;
6 #size-cells = <0x0>;
8 cpu-map {
45 compatible = "arm,cortex-a57";
47 enable-method = "psci";
49 i-cache-size = <0xC000>;
50 i-cache-line-size = <64>;
51 i-cache-sets = <256>;
52 d-cache-size = <0x8000>;
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/Linux-v6.1/Documentation/translations/zh_TW/arm64/
Dsilicon-errata.txt1 SPDX-License-Identifier: GPL-2.0
3 Chinese translated version of Documentation/arm64/silicon-errata.rst
15 ---------------------------------------------------------------------
16 Documentation/arm64/silicon-errata.rst 的中文翻譯
30 ---------------------------------------------------------------------
55 相應的內核配置（Kconfig）選項被加在 「內核特性（Kernel Features）」->
66 +----------------+-----------------+-----------------+-------------------------+
67 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
68 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
69 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
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/Linux-v6.1/Documentation/translations/zh_CN/arm64/
Dsilicon-errata.txt1 Chinese translated version of Documentation/arm64/silicon-errata.rst
12 ---------------------------------------------------------------------
13 Documentation/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
63 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
64 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
65 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
66 | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
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/Linux-v6.1/tools/perf/pmu-events/arch/arm64/
Dmapfile.csv10 # to tools/perf/pmu-events/arch/arm64/.
14 #Family-model,Version,Filename,EventType
15 0x00000000410fd020,v1,arm/cortex-a34,core
16 0x00000000410fd030,v1,arm/cortex-a53,core
17 0x00000000420f1000,v1,arm/cortex-a53,core
18 0x00000000410fd040,v1,arm/cortex-a35,core
19 0x00000000410fd050,v1,arm/cortex-a55,core
20 0x00000000410fd060,v1,arm/cortex-a65-e1,core
21 0x00000000410fd4a0,v1,arm/cortex-a65-e1,core
22 0x00000000410fd070,v1,arm/cortex-a57-a72,core
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/Linux-v6.1/arch/arm64/boot/dts/arm/
Djuno.dts4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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Djuno-r1.dts9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
18 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
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/Linux-v6.1/drivers/soc/tegra/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
63 # 64-bit ARM SoCs
75 Tegra124's "4+1" Cortex-A15 CPU complex.
85 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
88 and providing 256 CUDA cores. It supports hardware-accelerated en-
105 combination of Denver and Cortex-A57 CPU cores and a GPU based on
106 the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
108 multi-format support, ISP for image capture processing and BPMP for
/Linux-v6.1/arch/arm64/boot/dts/amazon/
Dalpine-v2.dtsi4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
46 #address-cells = <2>;
47 #size-cells = <0>;
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/Linux-v6.1/arch/arm64/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
234 ARM 64-bit (AArch64) Linux support.
244 depends on $(cc-option,-fpatchable-function-entry=2)
277 # VA_BITS - PAGE_SHIFT - 3
356 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
383 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
388 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
391 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
397 data cache clean-and-invalidate.
405 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
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/Linux-v6.1/tools/testing/kunit/qemu_configs/
Darm64.py12 extra_qemu_params=['-machine', 'virt', '-cpu', 'cortex-a57'])
/Linux-v6.1/Documentation/arm64/
Dsilicon-errata.rst10 so-called "errata", which can cause it to deviate from the architecture
32 cases (e.g. those cases that both require a non-secure workaround *and*
37 Features" -> "ARM errata workarounds via the alternatives framework".
39 CPU is detected. For less-intrusive workarounds, a Kconfig option is not
49 +----------------+-----------------+-----------------+-----------------------------+
53 +----------------+-----------------+-----------------+-----------------------------+
54 +----------------+-----------------+-----------------+-----------------------------+
55 | ARM | Cortex-A510 | #2457168 | ARM64_ERRATUM_2457168 |
56 +----------------+-----------------+-----------------+-----------------------------+
57 | ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 |
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/Linux-v6.1/arch/arm64/boot/dts/exynos/
Dexynos7.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
31 arm-pmu {
32 compatible = "arm,cortex-a57-pmu";
37 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
43 compatible = "fixed-clock";
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/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dmsm8994.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
13 interrupt-parent = <&intc>;
15 #address-cells = <2>;
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/Linux-v6.1/arch/arm64/kernel/
Dcpu_errata.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/arm-smccc.h>
24 if (!is_midr_in_range(midr, &entry->midr_range)) in is_affected_midr_range()
29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) in is_affected_midr_range()
30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) in is_affected_midr_range()
41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list); in is_affected_midr_range_list()
55 return model == entry->midr_range.model; in is_kryo_midr()
102 if (cap->capability == ARM64_WORKAROUND_1542419) in cpu_enable_trap_ctr_access()
135 if (regp->user_mask & ID_AA64ISAR1_EL1_BF16_MASK) in cpu_clear_bf16_from_user_emulation()
136 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; in cpu_clear_bf16_from_user_emulation()
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/Linux-v6.1/arch/arm64/kvm/hyp/vhe/
Dsysreg-sr.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2015 - ARM Ltd
7 #include <hyp/sysreg-sr.h>
54 * kvm_vcpu_load_sysregs_vhe - Load guest system registers to the physical CPU
66 struct kvm_cpu_context *guest_ctxt = &vcpu->arch.ctxt; in kvm_vcpu_load_sysregs_vhe()
69 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; in kvm_vcpu_load_sysregs_vhe()
75 * We must restore the 32-bit state before the sysregs, thanks in kvm_vcpu_load_sysregs_vhe()
76 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72). in kvm_vcpu_load_sysregs_vhe()
88 * kvm_vcpu_put_sysregs_vhe - Restore host system registers to the physical CPU
100 struct kvm_cpu_context *guest_ctxt = &vcpu->arch.ctxt; in kvm_vcpu_put_sysregs_vhe()
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/Linux-v6.1/Documentation/driver-api/thermal/
Dcpu-cooling-api.rst22 --------------------------------------------
30 "thermal-cpufreq-%x". This api can support multiple instances of cpufreq
42 the name "thermal-cpufreq-%x" linking it with a device tree node, in
54 This interface function unregisters the "thermal-cpufreq-%x" cooling device.
63 supported currently). This power model requires that the operating-points of
73 - The time the processor spends running, consuming dynamic power, as
76 - The voltage and frequency levels as a result of DVFS. The DVFS
78 - In running time the 'execution' behaviour (instruction types, memory
91 The detailed behaviour for f(run) could be modelled on-line. However,
92 in practice, such an on-line model has dependencies on a number of
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