1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8994.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8994.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/power/qcom-rpmpd.h>
11
12/ {
13	interrupt-parent = <&intc>;
14
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	aliases {
19		mmc1 = &sdhc1;
20		mmc2 = &sdhc2;
21	};
22
23	chosen { };
24
25	clocks {
26		xo_board: xo-board {
27			compatible = "fixed-clock";
28			#clock-cells = <0>;
29			clock-frequency = <19200000>;
30			clock-output-names = "xo_board";
31		};
32
33		sleep_clk: sleep-clk {
34			compatible = "fixed-clock";
35			#clock-cells = <0>;
36			clock-frequency = <32768>;
37			clock-output-names = "sleep_clk";
38		};
39	};
40
41	cpus {
42		#address-cells = <2>;
43		#size-cells = <0>;
44
45		CPU0: cpu@0 {
46			device_type = "cpu";
47			compatible = "arm,cortex-a53";
48			reg = <0x0 0x0>;
49			enable-method = "psci";
50			next-level-cache = <&L2_0>;
51			L2_0: l2-cache {
52				compatible = "cache";
53				cache-level = <2>;
54			};
55		};
56
57		CPU1: cpu@1 {
58			device_type = "cpu";
59			compatible = "arm,cortex-a53";
60			reg = <0x0 0x1>;
61			enable-method = "psci";
62			next-level-cache = <&L2_0>;
63		};
64
65		CPU2: cpu@2 {
66			device_type = "cpu";
67			compatible = "arm,cortex-a53";
68			reg = <0x0 0x2>;
69			enable-method = "psci";
70			next-level-cache = <&L2_0>;
71		};
72
73		CPU3: cpu@3 {
74			device_type = "cpu";
75			compatible = "arm,cortex-a53";
76			reg = <0x0 0x3>;
77			enable-method = "psci";
78			next-level-cache = <&L2_0>;
79		};
80
81		CPU4: cpu@100 {
82			device_type = "cpu";
83			compatible = "arm,cortex-a57";
84			reg = <0x0 0x100>;
85			enable-method = "psci";
86			next-level-cache = <&L2_1>;
87			L2_1: l2-cache {
88				compatible = "cache";
89				cache-level = <2>;
90			};
91		};
92
93		CPU5: cpu@101 {
94			device_type = "cpu";
95			compatible = "arm,cortex-a57";
96			reg = <0x0 0x101>;
97			enable-method = "psci";
98			next-level-cache = <&L2_1>;
99		};
100
101		CPU6: cpu@102 {
102			device_type = "cpu";
103			compatible = "arm,cortex-a57";
104			reg = <0x0 0x102>;
105			enable-method = "psci";
106			next-level-cache = <&L2_1>;
107		};
108
109		CPU7: cpu@103 {
110			device_type = "cpu";
111			compatible = "arm,cortex-a57";
112			reg = <0x0 0x103>;
113			enable-method = "psci";
114			next-level-cache = <&L2_1>;
115		};
116
117		cpu-map {
118			cluster0 {
119				core0 {
120					cpu = <&CPU0>;
121				};
122
123				core1 {
124					cpu = <&CPU1>;
125				};
126
127				core2 {
128					cpu = <&CPU2>;
129				};
130
131				core3 {
132					cpu = <&CPU3>;
133				};
134			};
135
136			cluster1 {
137				core0 {
138					cpu = <&CPU4>;
139				};
140
141				core1 {
142					cpu = <&CPU5>;
143				};
144
145				cpu6_map: core2 {
146					cpu = <&CPU6>;
147				};
148
149				cpu7_map: core3 {
150					cpu = <&CPU7>;
151				};
152			};
153		};
154	};
155
156	firmware {
157		scm {
158			compatible = "qcom,scm-msm8994", "qcom,scm";
159		};
160	};
161
162	memory@80000000 {
163		device_type = "memory";
164		/* We expect the bootloader to fill in the reg */
165		reg = <0 0x80000000 0 0>;
166	};
167
168	pmu {
169		compatible = "arm,cortex-a53-pmu";
170		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
171	};
172
173	psci {
174		compatible = "arm,psci-0.2";
175		method = "hvc";
176	};
177
178	reserved-memory {
179		#address-cells = <2>;
180		#size-cells = <2>;
181		ranges;
182
183		dfps_data_mem: dfps_data_mem@3400000 {
184			reg = <0 0x03400000 0 0x1000>;
185			no-map;
186		};
187
188		cont_splash_mem: memory@3401000 {
189			reg = <0 0x03401000 0 0x2200000>;
190			no-map;
191		};
192
193		smem_mem: smem_region@6a00000 {
194			reg = <0 0x06a00000 0 0x200000>;
195			no-map;
196		};
197
198		mpss_mem: memory@7000000 {
199			reg = <0 0x07000000 0 0x5a00000>;
200			no-map;
201		};
202
203		peripheral_region: memory@ca00000 {
204			reg = <0 0x0ca00000 0 0x1f00000>;
205			no-map;
206		};
207
208		rmtfs_mem: memory@c6400000 {
209			compatible = "qcom,rmtfs-mem";
210			reg = <0 0xc6400000 0 0x180000>;
211			no-map;
212
213			qcom,client-id = <1>;
214		};
215
216		mba_mem: memory@c6700000 {
217			reg = <0 0xc6700000 0 0x100000>;
218			no-map;
219		};
220
221		audio_mem: memory@c7000000 {
222			reg = <0 0xc7000000 0 0x800000>;
223			no-map;
224		};
225
226		adsp_mem: memory@c9400000 {
227			reg = <0 0xc9400000 0 0x3f00000>;
228			no-map;
229		};
230	};
231
232	smd {
233		compatible = "qcom,smd";
234		rpm {
235			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
236			qcom,ipc = <&apcs 8 0>;
237			qcom,smd-edge = <15>;
238			qcom,remote-pid = <6>;
239
240			rpm_requests: rpm-requests {
241				compatible = "qcom,rpm-msm8994";
242				qcom,smd-channels = "rpm_requests";
243
244				rpmcc: rpmcc {
245					compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
246					#clock-cells = <1>;
247				};
248
249				rpmpd: power-controller {
250					compatible = "qcom,msm8994-rpmpd";
251					#power-domain-cells = <1>;
252					operating-points-v2 = <&rpmpd_opp_table>;
253
254					rpmpd_opp_table: opp-table {
255						compatible = "operating-points-v2";
256
257						rpmpd_opp_ret: opp1 {
258							opp-level = <1>;
259						};
260						rpmpd_opp_svs_krait: opp2 {
261							opp-level = <2>;
262						};
263						rpmpd_opp_svs_soc: opp3 {
264							opp-level = <3>;
265						};
266						rpmpd_opp_nom: opp4 {
267							opp-level = <4>;
268						};
269						rpmpd_opp_turbo: opp5 {
270							opp-level = <5>;
271						};
272						rpmpd_opp_super_turbo: opp6 {
273							opp-level = <6>;
274						};
275					};
276				};
277			};
278		};
279	};
280
281	smem {
282		compatible = "qcom,smem";
283		memory-region = <&smem_mem>;
284		qcom,rpm-msg-ram = <&rpm_msg_ram>;
285		hwlocks = <&tcsr_mutex 3>;
286	};
287
288	smp2p-lpass {
289		compatible = "qcom,smp2p";
290		qcom,smem = <443>, <429>;
291
292		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
293
294		qcom,ipc = <&apcs 8 10>;
295
296		qcom,local-pid = <0>;
297		qcom,remote-pid = <2>;
298
299		adsp_smp2p_out: master-kernel {
300			qcom,entry-name = "master-kernel";
301			#qcom,smem-state-cells = <1>;
302		};
303
304		adsp_smp2p_in: slave-kernel {
305			qcom,entry-name = "slave-kernel";
306
307			interrupt-controller;
308			#interrupt-cells = <2>;
309		};
310	};
311
312	smp2p-modem {
313		compatible = "qcom,smp2p";
314		qcom,smem = <435>, <428>;
315
316		interrupt-parent = <&intc>;
317		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
318
319		qcom,ipc = <&apcs 8 14>;
320
321		qcom,local-pid = <0>;
322		qcom,remote-pid = <1>;
323
324		modem_smp2p_out: master-kernel {
325			qcom,entry-name = "master-kernel";
326			#qcom,smem-state-cells = <1>;
327		};
328
329		modem_smp2p_in: slave-kernel {
330			qcom,entry-name = "slave-kernel";
331
332			interrupt-controller;
333			#interrupt-cells = <2>;
334		};
335	};
336
337	soc: soc {
338
339		#address-cells = <1>;
340		#size-cells = <1>;
341		ranges = <0 0 0 0xffffffff>;
342		compatible = "simple-bus";
343
344		intc: interrupt-controller@f9000000 {
345			compatible = "qcom,msm-qgic2";
346			interrupt-controller;
347			#interrupt-cells = <3>;
348			reg = <0xf9000000 0x1000>,
349			      <0xf9002000 0x1000>;
350		};
351
352		apcs: mailbox@f900d000 {
353			compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
354			reg = <0xf900d000 0x2000>;
355			#mbox-cells = <1>;
356		};
357
358		watchdog@f9017000 {
359			compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt";
360			reg = <0xf9017000 0x1000>;
361			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
362				     <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
363			clocks = <&sleep_clk>;
364			timeout-sec = <10>;
365		};
366
367		timer@f9020000 {
368			#address-cells = <1>;
369			#size-cells = <1>;
370			ranges;
371			compatible = "arm,armv7-timer-mem";
372			reg = <0xf9020000 0x1000>;
373
374			frame@f9021000 {
375				frame-number = <0>;
376				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
377					     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
378				reg = <0xf9021000 0x1000>,
379				      <0xf9022000 0x1000>;
380			};
381
382			frame@f9023000 {
383				frame-number = <1>;
384				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
385				reg = <0xf9023000 0x1000>;
386				status = "disabled";
387			};
388
389			frame@f9024000 {
390				frame-number = <2>;
391				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
392				reg = <0xf9024000 0x1000>;
393				status = "disabled";
394			};
395
396			frame@f9025000 {
397				frame-number = <3>;
398				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
399				reg = <0xf9025000 0x1000>;
400				status = "disabled";
401			};
402
403			frame@f9026000 {
404				frame-number = <4>;
405				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
406				reg = <0xf9026000 0x1000>;
407				status = "disabled";
408			};
409
410			frame@f9027000 {
411				frame-number = <5>;
412				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
413				reg = <0xf9027000 0x1000>;
414				status = "disabled";
415			};
416
417			frame@f9028000 {
418				frame-number = <6>;
419				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
420				reg = <0xf9028000 0x1000>;
421				status = "disabled";
422			};
423		};
424
425		usb3: usb@f92f8800 {
426			compatible = "qcom,msm8994-dwc3", "qcom,dwc3";
427			reg = <0xf92f8800 0x400>;
428			#address-cells = <1>;
429			#size-cells = <1>;
430			ranges;
431
432			clocks = <&gcc GCC_USB30_MASTER_CLK>,
433				 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
434				 <&gcc GCC_USB30_SLEEP_CLK>,
435				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
436			clock-names = "core",
437				      "iface",
438				      "sleep",
439				      "mock_utmi";
440
441			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
442					  <&gcc GCC_USB30_MASTER_CLK>;
443			assigned-clock-rates = <19200000>, <120000000>;
444
445			power-domains = <&gcc USB30_GDSC>;
446			qcom,select-utmi-as-pipe-clk;
447
448			usb@f9200000 {
449				compatible = "snps,dwc3";
450				reg = <0xf9200000 0xcc00>;
451				interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
452				snps,dis_u2_susphy_quirk;
453				snps,dis_enblslpm_quirk;
454				maximum-speed = "high-speed";
455				dr_mode = "peripheral";
456			};
457		};
458
459		sdhc1: mmc@f9824900 {
460			compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
461			reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
462			reg-names = "hc", "core";
463
464			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
465				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
466			interrupt-names = "hc_irq", "pwr_irq";
467
468			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
469				 <&gcc GCC_SDCC1_APPS_CLK>,
470				 <&xo_board>;
471			clock-names = "iface", "core", "xo";
472
473			pinctrl-names = "default", "sleep";
474			pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
475			pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
476
477			bus-width = <8>;
478			non-removable;
479			status = "disabled";
480		};
481
482		sdhc2: mmc@f98a4900 {
483			compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
484			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
485			reg-names = "hc", "core";
486
487			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
488				<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
489			interrupt-names = "hc_irq", "pwr_irq";
490
491			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
492				 <&gcc GCC_SDCC2_APPS_CLK>,
493				 <&xo_board>;
494			clock-names = "iface", "core", "xo";
495
496			pinctrl-names = "default", "sleep";
497			pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
498			pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
499
500			cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
501			bus-width = <4>;
502			status = "disabled";
503		};
504
505		blsp1_dma: dma-controller@f9904000 {
506			compatible = "qcom,bam-v1.7.0";
507			reg = <0xf9904000 0x19000>;
508			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
509			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
510			clock-names = "bam_clk";
511			#dma-cells = <1>;
512			qcom,ee = <0>;
513			qcom,controlled-remotely;
514			num-channels = <24>;
515			qcom,num-ees = <4>;
516		};
517
518		blsp1_uart2: serial@f991e000 {
519			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
520			reg = <0xf991e000 0x1000>;
521			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
522			clock-names = "core", "iface";
523			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
524				 <&gcc GCC_BLSP1_AHB_CLK>;
525			pinctrl-names = "default", "sleep";
526			pinctrl-0 = <&blsp1_uart2_default>;
527			pinctrl-1 = <&blsp1_uart2_sleep>;
528			status = "disabled";
529		};
530
531		blsp1_i2c1: i2c@f9923000 {
532			compatible = "qcom,i2c-qup-v2.2.1";
533			reg = <0xf9923000 0x500>;
534			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
535			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
536				 <&gcc GCC_BLSP1_AHB_CLK>;
537			clock-names = "core", "iface";
538			clock-frequency = <400000>;
539			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
540			dma-names = "tx", "rx";
541			pinctrl-names = "default", "sleep";
542			pinctrl-0 = <&i2c1_default>;
543			pinctrl-1 = <&i2c1_sleep>;
544			#address-cells = <1>;
545			#size-cells = <0>;
546			status = "disabled";
547		};
548
549		blsp1_spi1: spi@f9923000 {
550			compatible = "qcom,spi-qup-v2.2.1";
551			reg = <0xf9923000 0x500>;
552			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
553			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
554				 <&gcc GCC_BLSP1_AHB_CLK>;
555			clock-names = "core", "iface";
556			spi-max-frequency = <19200000>;
557			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
558			dma-names = "tx", "rx";
559			pinctrl-names = "default", "sleep";
560			pinctrl-0 = <&blsp1_spi1_default>;
561			pinctrl-1 = <&blsp1_spi1_sleep>;
562			#address-cells = <1>;
563			#size-cells = <0>;
564			status = "disabled";
565		};
566
567		blsp1_i2c2: i2c@f9924000 {
568			compatible = "qcom,i2c-qup-v2.2.1";
569			reg = <0xf9924000 0x500>;
570			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
571			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
572				 <&gcc GCC_BLSP1_AHB_CLK>;
573			clock-names = "core", "iface";
574			clock-frequency = <400000>;
575			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
576			dma-names = "tx", "rx";
577			pinctrl-names = "default", "sleep";
578			pinctrl-0 = <&i2c2_default>;
579			pinctrl-1 = <&i2c2_sleep>;
580			#address-cells = <1>;
581			#size-cells = <0>;
582			status = "disabled";
583		};
584
585		/* I2C3 doesn't exist */
586
587		blsp1_i2c4: i2c@f9926000 {
588			compatible = "qcom,i2c-qup-v2.2.1";
589			reg = <0xf9926000 0x500>;
590			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
591			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
592				 <&gcc GCC_BLSP1_AHB_CLK>;
593			clock-names = "core", "iface";
594			clock-frequency = <400000>;
595			dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
596			dma-names = "tx", "rx";
597			pinctrl-names = "default", "sleep";
598			pinctrl-0 = <&i2c4_default>;
599			pinctrl-1 = <&i2c4_sleep>;
600			#address-cells = <1>;
601			#size-cells = <0>;
602			status = "disabled";
603		};
604
605		blsp1_i2c5: i2c@f9927000 {
606			compatible = "qcom,i2c-qup-v2.2.1";
607			reg = <0xf9927000 0x500>;
608			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
609			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
610				 <&gcc GCC_BLSP1_AHB_CLK>;
611			clock-names = "core", "iface";
612			clock-frequency = <400000>;
613			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
614			dma-names = "tx", "rx";
615			pinctrl-names = "default", "sleep";
616			pinctrl-0 = <&i2c5_default>;
617			pinctrl-1 = <&i2c5_sleep>;
618			#address-cells = <1>;
619			#size-cells = <0>;
620			status = "disabled";
621		};
622
623		blsp1_i2c6: i2c@f9928000 {
624			compatible = "qcom,i2c-qup-v2.2.1";
625			reg = <0xf9928000 0x500>;
626			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
627			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
628				 <&gcc GCC_BLSP1_AHB_CLK>;
629			clock-names = "core", "iface";
630			clock-frequency = <400000>;
631			dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
632			dma-names = "tx", "rx";
633			pinctrl-names = "default", "sleep";
634			pinctrl-0 = <&i2c6_default>;
635			pinctrl-1 = <&i2c6_sleep>;
636			#address-cells = <1>;
637			#size-cells = <0>;
638			status = "disabled";
639		};
640
641		blsp2_dma: dma-controller@f9944000 {
642			compatible = "qcom,bam-v1.7.0";
643			reg = <0xf9944000 0x19000>;
644			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
645			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
646			clock-names = "bam_clk";
647			#dma-cells = <1>;
648			qcom,ee = <0>;
649			qcom,controlled-remotely;
650			num-channels = <24>;
651			qcom,num-ees = <4>;
652		};
653
654		blsp2_uart2: serial@f995e000 {
655			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
656			reg = <0xf995e000 0x1000>;
657			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
658			clock-names = "core", "iface";
659			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
660					<&gcc GCC_BLSP2_AHB_CLK>;
661			dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
662			dma-names = "tx", "rx";
663			pinctrl-names = "default", "sleep";
664			pinctrl-0 = <&blsp2_uart2_default>;
665			pinctrl-1 = <&blsp2_uart2_sleep>;
666			status = "disabled";
667		};
668
669		blsp2_i2c1: i2c@f9963000 {
670			compatible = "qcom,i2c-qup-v2.2.1";
671			reg = <0xf9963000 0x500>;
672			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
673			clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
674				 <&gcc GCC_BLSP2_AHB_CLK>;
675			clock-names = "core", "iface";
676			clock-frequency = <400000>;
677			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
678			dma-names = "tx", "rx";
679			pinctrl-names = "default", "sleep";
680			pinctrl-0 = <&i2c7_default>;
681			pinctrl-1 = <&i2c7_sleep>;
682			#address-cells = <1>;
683			#size-cells = <0>;
684			status = "disabled";
685		};
686
687		blsp2_spi4: spi@f9966000 {
688			compatible = "qcom,spi-qup-v2.2.1";
689			reg = <0xf9966000 0x500>;
690			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
691			clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
692				 <&gcc GCC_BLSP2_AHB_CLK>;
693			clock-names = "core", "iface";
694			spi-max-frequency = <19200000>;
695			dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
696			dma-names = "tx", "rx";
697			pinctrl-names = "default", "sleep";
698			pinctrl-0 = <&blsp2_spi10_default>;
699			pinctrl-1 = <&blsp2_spi10_sleep>;
700			#address-cells = <1>;
701			#size-cells = <0>;
702			status = "disabled";
703		};
704
705		blsp2_i2c5: i2c@f9967000 {
706			compatible = "qcom,i2c-qup-v2.2.1";
707			reg = <0xf9967000 0x500>;
708			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
709			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
710				 <&gcc GCC_BLSP2_AHB_CLK>;
711			clock-names = "core", "iface";
712			clock-frequency = <355000>;
713			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
714			dma-names = "tx", "rx";
715			pinctrl-names = "default", "sleep";
716			pinctrl-0 = <&i2c11_default>;
717			pinctrl-1 = <&i2c11_sleep>;
718			#address-cells = <1>;
719			#size-cells = <0>;
720			status = "disabled";
721		};
722
723		gcc: clock-controller@fc400000 {
724			compatible = "qcom,gcc-msm8994";
725			#clock-cells = <1>;
726			#reset-cells = <1>;
727			#power-domain-cells = <1>;
728			reg = <0xfc400000 0x2000>;
729
730			clock-names = "xo", "sleep";
731			clocks = <&xo_board>, <&sleep_clk>;
732		};
733
734		rpm_msg_ram: sram@fc428000 {
735			compatible = "qcom,rpm-msg-ram";
736			reg = <0xfc428000 0x4000>;
737		};
738
739		restart@fc4ab000 {
740			compatible = "qcom,pshold";
741			reg = <0xfc4ab000 0x4>;
742		};
743
744		spmi_bus: spmi@fc4c0000 {
745			compatible = "qcom,spmi-pmic-arb";
746			reg = <0xfc4cf000 0x1000>,
747			      <0xfc4cb000 0x1000>,
748			      <0xfc4ca000 0x1000>;
749			reg-names = "core", "intr", "cnfg";
750			interrupt-names = "periph_irq";
751			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
752			qcom,ee = <0>;
753			qcom,channel = <0>;
754			#address-cells = <2>;
755			#size-cells = <0>;
756			interrupt-controller;
757			#interrupt-cells = <4>;
758		};
759
760		tcsr_mutex: hwlock@fd484000 {
761			compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex";
762			reg = <0xfd484000 0x1000>;
763			#hwlock-cells = <1>;
764		};
765
766		tlmm: pinctrl@fd510000 {
767			compatible = "qcom,msm8994-pinctrl";
768			reg = <0xfd510000 0x4000>;
769			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
770			gpio-controller;
771			gpio-ranges = <&tlmm 0 0 146>;
772			#gpio-cells = <2>;
773			interrupt-controller;
774			#interrupt-cells = <2>;
775
776			blsp1_uart2_default: blsp1-uart2-default {
777				function = "blsp_uart2";
778				pins = "gpio4", "gpio5";
779				drive-strength = <16>;
780				bias-disable;
781			};
782
783			blsp1_uart2_sleep: blsp1-uart2-sleep {
784				function = "gpio";
785				pins = "gpio4", "gpio5";
786				drive-strength = <2>;
787				bias-pull-down;
788			};
789
790			blsp2_uart2_default: blsp2-uart2-default {
791				function = "blsp_uart8";
792				pins = "gpio45", "gpio46",
793						"gpio47", "gpio48";
794				drive-strength = <16>;
795				bias-disable;
796			};
797
798			blsp2_uart2_sleep: blsp2-uart2-sleep {
799				function = "gpio";
800				pins = "gpio45", "gpio46",
801						"gpio47", "gpio48";
802				drive-strength = <2>;
803				bias-disable;
804			};
805
806			i2c1_default: i2c1-default {
807				function = "blsp_i2c1";
808				pins = "gpio2", "gpio3";
809				drive-strength = <2>;
810				bias-disable;
811			};
812
813			i2c1_sleep: i2c1-sleep {
814				function = "gpio";
815				pins = "gpio2", "gpio3";
816				drive-strength = <2>;
817				bias-disable;
818			};
819
820			i2c2_default: i2c2-default {
821				function = "blsp_i2c2";
822				pins = "gpio6", "gpio7";
823				drive-strength = <2>;
824				bias-disable;
825			};
826
827			i2c2_sleep: i2c2-sleep {
828				function = "gpio";
829				pins = "gpio6", "gpio7";
830				drive-strength = <2>;
831				bias-disable;
832			};
833
834			i2c4_default: i2c4-default {
835				function = "blsp_i2c4";
836				pins = "gpio19", "gpio20";
837				drive-strength = <2>;
838				bias-disable;
839			};
840
841			i2c4_sleep: i2c4-sleep {
842				function = "gpio";
843				pins = "gpio19", "gpio20";
844				drive-strength = <2>;
845				bias-pull-down;
846				input-enable;
847			};
848
849			i2c5_default: i2c5-default {
850				function = "blsp_i2c5";
851				pins = "gpio23", "gpio24";
852				drive-strength = <2>;
853				bias-disable;
854			};
855
856			i2c5_sleep: i2c5-sleep {
857				function = "gpio";
858				pins = "gpio23", "gpio24";
859				drive-strength = <2>;
860				bias-disable;
861			};
862
863			i2c6_default: i2c6-default {
864				function = "blsp_i2c6";
865				pins = "gpio28", "gpio27";
866				drive-strength = <2>;
867				bias-disable;
868			};
869
870			i2c6_sleep: i2c6-sleep {
871				function = "gpio";
872				pins = "gpio28", "gpio27";
873				drive-strength = <2>;
874				bias-disable;
875			};
876
877			i2c7_default: i2c7-default {
878				function = "blsp_i2c7";
879				pins = "gpio44", "gpio43";
880				drive-strength = <2>;
881				bias-disable;
882			};
883
884			i2c7_sleep: i2c7-sleep {
885				function = "gpio";
886				pins = "gpio44", "gpio43";
887				drive-strength = <2>;
888				bias-disable;
889			};
890
891			blsp2_spi10_default: blsp2-spi10-default {
892				default {
893					function = "blsp_spi10";
894					pins = "gpio53", "gpio54", "gpio55";
895					drive-strength = <10>;
896					bias-pull-down;
897				};
898				cs {
899					function = "gpio";
900					pins = "gpio55";
901					drive-strength = <2>;
902					bias-disable;
903				};
904			};
905
906			blsp2_spi10_sleep: blsp2-spi10-sleep {
907				pins = "gpio53", "gpio54", "gpio55";
908				drive-strength = <2>;
909				bias-disable;
910			};
911
912			i2c11_default: i2c11-default {
913				function = "blsp_i2c11";
914				pins = "gpio83", "gpio84";
915				drive-strength = <2>;
916				bias-disable;
917			};
918
919			i2c11_sleep: i2c11-sleep {
920				function = "gpio";
921				pins = "gpio83", "gpio84";
922				drive-strength = <2>;
923				bias-disable;
924			};
925
926			blsp1_spi1_default: blsp1-spi1-default {
927				default {
928					function = "blsp_spi1";
929					pins = "gpio0", "gpio1", "gpio3";
930					drive-strength = <10>;
931					bias-pull-down;
932				};
933				cs {
934					function = "gpio";
935					pins = "gpio8";
936					drive-strength = <2>;
937					bias-disable;
938				};
939			};
940
941			blsp1_spi1_sleep: blsp1-spi1-sleep {
942				pins = "gpio0", "gpio1", "gpio3";
943				drive-strength = <2>;
944				bias-disable;
945			};
946
947			sdc1_clk_on: clk-on {
948				pins = "sdc1_clk";
949				bias-disable;
950				drive-strength = <16>;
951			};
952
953			sdc1_clk_off: clk-off {
954				pins = "sdc1_clk";
955				bias-disable;
956				drive-strength = <2>;
957			};
958
959			sdc1_cmd_on: cmd-on {
960				pins = "sdc1_cmd";
961				bias-pull-up;
962				drive-strength = <8>;
963			};
964
965			sdc1_cmd_off: cmd-off {
966				pins = "sdc1_cmd";
967				bias-pull-up;
968				drive-strength = <2>;
969			};
970
971			sdc1_data_on: data-on {
972				pins = "sdc1_data";
973				bias-pull-up;
974				drive-strength = <8>;
975			};
976
977			sdc1_data_off: data-off {
978				pins = "sdc1_data";
979				bias-pull-up;
980				drive-strength = <2>;
981			};
982
983			sdc1_rclk_on: rclk-on {
984				pins = "sdc1_rclk";
985				bias-pull-down;
986			};
987
988			sdc1_rclk_off: rclk-off {
989				pins = "sdc1_rclk";
990				bias-pull-down;
991			};
992
993			sdc2_clk_on: sdc2-clk-on {
994				pins = "sdc2_clk";
995				bias-disable;
996				drive-strength = <10>;
997			};
998
999			sdc2_clk_off: sdc2-clk-off {
1000				pins = "sdc2_clk";
1001				bias-disable;
1002				drive-strength = <2>;
1003			};
1004
1005			sdc2_cmd_on: sdc2-cmd-on {
1006				pins = "sdc2_cmd";
1007				bias-pull-up;
1008				drive-strength = <10>;
1009			};
1010
1011			sdc2_cmd_off: sdc2-cmd-off {
1012				pins = "sdc2_cmd";
1013				bias-pull-up;
1014				drive-strength = <2>;
1015			};
1016
1017			sdc2_data_on: sdc2-data-on {
1018				pins = "sdc2_data";
1019				bias-pull-up;
1020				drive-strength = <10>;
1021			};
1022
1023			sdc2_data_off: sdc2-data-off {
1024				pins = "sdc2_data";
1025				bias-pull-up;
1026				drive-strength = <2>;
1027			};
1028		};
1029
1030		mmcc: clock-controller@fd8c0000 {
1031			compatible = "qcom,mmcc-msm8994";
1032			reg = <0xfd8c0000 0x5200>;
1033			#clock-cells = <1>;
1034			#reset-cells = <1>;
1035			#power-domain-cells = <1>;
1036
1037			clock-names = "xo",
1038				      "gpll0",
1039				      "mmssnoc_ahb",
1040				      "oxili_gfx3d_clk_src",
1041				      "dsi0pll",
1042				      "dsi0pllbyte",
1043				      "dsi1pll",
1044				      "dsi1pllbyte",
1045				      "hdmipll";
1046			clocks = <&xo_board>,
1047				 <&gcc GPLL0_OUT_MMSSCC>,
1048				 <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>,
1049				 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1050				 <0>,
1051				 <0>,
1052				 <0>,
1053				 <0>,
1054				 <0>;
1055
1056			assigned-clocks = <&mmcc MMPLL0_PLL>,
1057					  <&mmcc MMPLL1_PLL>,
1058					  <&mmcc MMPLL3_PLL>,
1059					  <&mmcc MMPLL4_PLL>,
1060					  <&mmcc MMPLL5_PLL>;
1061			assigned-clock-rates = <800000000>,
1062					       <1167000000>,
1063					       <1020000000>,
1064					       <960000000>,
1065					       <600000000>;
1066		};
1067
1068		ocmem: sram@fdd00000 {
1069			compatible = "qcom,msm8974-ocmem";
1070			reg = <0xfdd00000 0x2000>,
1071			      <0xfec00000 0x200000>;
1072			reg-names = "ctrl", "mem";
1073			ranges = <0 0xfec00000 0x200000>;
1074			clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1075				 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
1076			clock-names = "core", "iface";
1077
1078			#address-cells = <1>;
1079			#size-cells = <1>;
1080
1081			gmu_sram: gmu-sram@0 {
1082				reg = <0x0 0x180000>;
1083			};
1084		};
1085	};
1086
1087	timer: timer {
1088		compatible = "arm,armv8-timer";
1089		interrupts = <GIC_PPI 2 0xff08>,
1090			     <GIC_PPI 3 0xff08>,
1091			     <GIC_PPI 4 0xff08>,
1092			     <GIC_PPI 1 0xff08>;
1093	};
1094
1095	vph_pwr: vph-pwr-regulator {
1096		compatible = "regulator-fixed";
1097		regulator-name = "vph_pwr";
1098
1099		regulator-min-microvolt = <3600000>;
1100		regulator-max-microvolt = <3600000>;
1101
1102		regulator-always-on;
1103	};
1104};
1105
1106