Lines Matching +full:cortex +full:- +full:a57
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
88 - apple,icestorm
89 - apple,firestorm
90 - arm,arm710t
91 - arm,arm720t
92 - arm,arm740t
93 - arm,arm7ej-s
94 - arm,arm7tdmi
95 - arm,arm7tdmi-s
96 - arm,arm9es
97 - arm,arm9ej-s
98 - arm,arm920t
99 - arm,arm922t
100 - arm,arm925
101 - arm,arm926e-s
102 - arm,arm926ej-s
103 - arm,arm940t
104 - arm,arm946e-s
105 - arm,arm966e-s
106 - arm,arm968e-s
107 - arm,arm9tdmi
108 - arm,arm1020e
109 - arm,arm1020t
110 - arm,arm1022e
111 - arm,arm1026ej-s
112 - arm,arm1136j-s
113 - arm,arm1136jf-s
114 - arm,arm1156t2-s
115 - arm,arm1156t2f-s
116 - arm,arm1176jzf
117 - arm,arm1176jz-s
118 - arm,arm1176jzf-s
119 - arm,arm11mpcore
120 - arm,armv8 # Only for s/w models
121 - arm,cortex-a5
122 - arm,cortex-a7
123 - arm,cortex-a8
124 - arm,cortex-a9
125 - arm,cortex-a12
126 - arm,cortex-a15
127 - arm,cortex-a17
128 - arm,cortex-a32
129 - arm,cortex-a34
130 - arm,cortex-a35
131 - arm,cortex-a53
132 - arm,cortex-a55
133 - arm,cortex-a57
134 - arm,cortex-a65
135 - arm,cortex-a72
136 - arm,cortex-a73
137 - arm,cortex-a75
138 - arm,cortex-a76
139 - arm,cortex-a77
140 - arm,cortex-a78
141 - arm,cortex-a78ae
142 - arm,cortex-a510
143 - arm,cortex-a710
144 - arm,cortex-m0
145 - arm,cortex-m0+
146 - arm,cortex-m1
147 - arm,cortex-m3
148 - arm,cortex-m4
149 - arm,cortex-r4
150 - arm,cortex-r5
151 - arm,cortex-r7
152 - arm,cortex-x1
153 - arm,cortex-x2
154 - arm,neoverse-e1
155 - arm,neoverse-n1
156 - arm,neoverse-n2
157 - arm,neoverse-v1
158 - brcm,brahma-b15
159 - brcm,brahma-b53
160 - brcm,vulcan
161 - cavium,thunder
162 - cavium,thunder2
163 - faraday,fa526
164 - intel,sa110
165 - intel,sa1100
166 - marvell,feroceon
167 - marvell,mohawk
168 - marvell,pj4a
169 - marvell,pj4b
170 - marvell,sheeva-v5
171 - marvell,sheeva-v7
172 - nvidia,tegra132-denver
173 - nvidia,tegra186-denver
174 - nvidia,tegra194-carmel
175 - qcom,krait
176 - qcom,kryo
177 - qcom,kryo240
178 - qcom,kryo250
179 - qcom,kryo260
180 - qcom,kryo280
181 - qcom,kryo385
182 - qcom,kryo468
183 - qcom,kryo485
184 - qcom,kryo560
185 - qcom,kryo570
186 - qcom,kryo685
187 - qcom,kryo780
188 - qcom,scorpion
190 enable-method:
193 # On ARM v8 64-bit this property is required
194 - enum:
195 - psci
196 - spin-table
197 # On ARM 32-bit systems this property is optional
198 - enum:
199 - actions,s500-smp
200 - allwinner,sun6i-a31
201 - allwinner,sun8i-a23
202 - allwinner,sun9i-a80-smp
203 - allwinner,sun8i-a83t-smp
204 - amlogic,meson8-smp
205 - amlogic,meson8b-smp
206 - arm,realview-smp
207 - aspeed,ast2600-smp
208 - brcm,bcm11351-cpu-method
209 - brcm,bcm23550
210 - brcm,bcm2836-smp
211 - brcm,bcm63138
212 - brcm,bcm-nsp-smp
213 - brcm,brahma-b15
214 - marvell,armada-375-smp
215 - marvell,armada-380-smp
216 - marvell,armada-390-smp
217 - marvell,armada-xp-smp
218 - marvell,98dx3236-smp
219 - marvell,mmp3-smp
220 - mediatek,mt6589-smp
221 - mediatek,mt81xx-tz-smp
222 - qcom,gcc-msm8660
223 - qcom,kpss-acc-v1
224 - qcom,kpss-acc-v2
225 - qcom,msm8226-smp
226 - qcom,msm8909-smp
227 # Only valid on ARM 32-bit, see above for ARM v8 64-bit
228 - qcom,msm8916-smp
229 - renesas,apmu
230 - renesas,r9a06g032-smp
231 - rockchip,rk3036-smp
232 - rockchip,rk3066-smp
233 - socionext,milbeaut-m10v-smp
234 - ste,dbx500-smp
235 - ti,am3352
236 - ti,am4372
238 cpu-release-addr:
240 - $ref: '/schemas/types.yaml#/definitions/uint32'
241 - $ref: '/schemas/types.yaml#/definitions/uint64'
243 The DT specification defines this as 64-bit always, but some 32-bit Arm
244 systems have used a 32-bit value which must be supported.
245 Required for systems that have an "enable-method"
246 property value of "spin-table".
248 cpu-idle-states:
249 $ref: '/schemas/types.yaml#/definitions/phandle-array'
254 by this cpu (see ./idle-states.yaml).
256 capacity-dmips-mhz:
258 u32 value representing CPU capacity (see ./cpu-capacity.txt) in
259 DMIPS/MHz, relative to highest capacity-dmips-mhz
262 cci-control-port: true
264 dynamic-power-coefficient:
275 calculate the dynamic power as below -
277 Pdyn = dynamic-power-coefficient * V^2 * f
281 performance-domains:
286 dvfs/performance-domain.yaml.
288 power-domains:
293 power-domain-names:
296 power-domains property.
306 Required for systems that have an "enable-method" property
307 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
316 Required for systems that have an "enable-method" property
317 value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
318 "qcom,msm8916-smp".
320 * arm/msm/qcom,kpss-acc.txt
327 Optional for systems that have an "enable-method"
328 property value of "rockchip,rk3066-smp"
330 the cpu-core power-domains.
332 secondary-boot-reg:
335 Required for systems that have an "enable-method" property value of
336 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
342 The secondary-boot-reg property is a u32 value that specifies the
349 # If the enable-method property contains one of those values
351 enable-method:
354 - brcm,bcm11351-cpu-method
355 - brcm,bcm23550
356 - brcm,bcm-nsp-smp
357 # and if enable-method is present
359 - enable-method
363 - secondary-boot-reg
366 - device_type
367 - reg
368 - compatible
371 rockchip,pmu: [enable-method]
376 - |
378 #size-cells = <0>;
379 #address-cells = <1>;
383 compatible = "arm,cortex-a15";
389 compatible = "arm,cortex-a15";
395 compatible = "arm,cortex-a7";
401 compatible = "arm,cortex-a7";
406 - |
407 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
409 #size-cells = <0>;
410 #address-cells = <1>;
414 compatible = "arm,cortex-a8";
419 - |
420 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
422 #size-cells = <0>;
423 #address-cells = <1>;
427 compatible = "arm,arm926ej-s";
432 - |
433 // Example 4 (ARM Cortex-A57 64-bit system):
435 #size-cells = <0>;
436 #address-cells = <2>;
440 compatible = "arm,cortex-a57";
442 enable-method = "spin-table";
443 cpu-release-addr = <0 0x20000000>;
448 compatible = "arm,cortex-a57";
450 enable-method = "spin-table";
451 cpu-release-addr = <0 0x20000000>;
456 compatible = "arm,cortex-a57";
458 enable-method = "spin-table";
459 cpu-release-addr = <0 0x20000000>;
464 compatible = "arm,cortex-a57";
466 enable-method = "spin-table";
467 cpu-release-addr = <0 0x20000000>;
472 compatible = "arm,cortex-a57";
474 enable-method = "spin-table";
475 cpu-release-addr = <0 0x20000000>;
480 compatible = "arm,cortex-a57";
482 enable-method = "spin-table";
483 cpu-release-addr = <0 0x20000000>;
488 compatible = "arm,cortex-a57";
490 enable-method = "spin-table";
491 cpu-release-addr = <0 0x20000000>;
496 compatible = "arm,cortex-a57";
498 enable-method = "spin-table";
499 cpu-release-addr = <0 0x20000000>;
504 compatible = "arm,cortex-a57";
506 enable-method = "spin-table";
507 cpu-release-addr = <0 0x20000000>;
512 compatible = "arm,cortex-a57";
514 enable-method = "spin-table";
515 cpu-release-addr = <0 0x20000000>;
520 compatible = "arm,cortex-a57";
522 enable-method = "spin-table";
523 cpu-release-addr = <0 0x20000000>;
528 compatible = "arm,cortex-a57";
530 enable-method = "spin-table";
531 cpu-release-addr = <0 0x20000000>;
536 compatible = "arm,cortex-a57";
538 enable-method = "spin-table";
539 cpu-release-addr = <0 0x20000000>;
544 compatible = "arm,cortex-a57";
546 enable-method = "spin-table";
547 cpu-release-addr = <0 0x20000000>;
552 compatible = "arm,cortex-a57";
554 enable-method = "spin-table";
555 cpu-release-addr = <0 0x20000000>;
560 compatible = "arm,cortex-a57";
562 enable-method = "spin-table";
563 cpu-release-addr = <0 0x20000000>;