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/Linux-v6.6/Documentation/devicetree/bindings/clock/
Dsamsung,exynos7885-clock.yaml23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
24 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
81 - description: CMU_CORE bus clock (from CMU_TOP)
82 - description: CCI clock (from CMU_TOP)
83 - description: G3D clock (from CMU_TOP)
103 - description: CMU_FSYS bus clock (from CMU_TOP)
104 - description: MMC_CARD clock (from CMU_TOP)
105 - description: MMC_EMBD clock (from CMU_TOP)
106 - description: MMC_SDIO clock (from CMU_TOP)
107 - description: USB30DRD clock (from CMU_TOP)
[all …]
Dsamsung,exynos850-clock.yaml23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
24 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
88 - description: CMU_APM bus clock (from CMU_TOP)
106 - description: AUD clock (from CMU_TOP)
142 - description: CMU_CORE bus clock (from CMU_TOP)
143 - description: CCI clock (from CMU_TOP)
144 - description: eMMC clock (from CMU_TOP)
145 - description: SSS clock (from CMU_TOP)
166 - description: DPU clock (from CMU_TOP)
184 - description: G3D clock (from CMU_TOP)
[all …]
Dsamsung,exynosautov9-clock.yaml23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
25 derived from CMU_TOP.
87 - description: CMU_BUSMC bus clock (from CMU_TOP)
105 - description: CMU_CORE bus clock (from CMU_TOP)
123 - description: CMU_FSYS0 bus clock (from CMU_TOP)
124 - description: CMU_FSYS0 pcie clock (from CMU_TOP)
143 - description: CMU_FSYS1 bus clock (from CMU_TOP)
144 - description: CMU_FSYS1 mmc card clock (from CMU_TOP)
145 - description: CMU_FSYS1 usb clock (from CMU_TOP)
165 - description: CMU_FSYS2 bus clock (from CMU_TOP)
[all …]
Dsamsung,exynos5433-clock.yaml26 # CMU_TOP which generates clocks for
/Linux-v6.6/arch/arm64/boot/dts/exynos/
Dexynos7885.dtsi198 <&cmu_top CLK_DOUT_PERI_BUS>,
199 <&cmu_top CLK_DOUT_PERI_SPI0>,
200 <&cmu_top CLK_DOUT_PERI_SPI1>,
201 <&cmu_top CLK_DOUT_PERI_UART0>,
202 <&cmu_top CLK_DOUT_PERI_UART1>,
203 <&cmu_top CLK_DOUT_PERI_UART2>,
204 <&cmu_top CLK_DOUT_PERI_USI0>,
205 <&cmu_top CLK_DOUT_PERI_USI1>,
206 <&cmu_top CLK_DOUT_PERI_USI2>;
225 <&cmu_top CLK_DOUT_CORE_BUS>,
[all …]
Dexynos5433-bus.dtsi12 clocks = <&cmu_top CLK_ACLK_G2D_400>;
20 clocks = <&cmu_top CLK_ACLK_G2D_266>;
28 clocks = <&cmu_top CLK_ACLK_GSCL_333>;
36 clocks = <&cmu_top CLK_ACLK_HEVC_400>;
44 clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>;
52 clocks = <&cmu_top CLK_ACLK_MFC_400>;
60 clocks = <&cmu_top CLK_ACLK_MSCL_400>;
68 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
76 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
Dexynos5433-tm2-common.dtsi229 <&cmu_top CLK_MOUT_AUD_PLL>,
230 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
231 <&cmu_top CLK_MOUT_SCLK_AUDIO0>,
232 <&cmu_top CLK_MOUT_SCLK_AUDIO1>,
233 <&cmu_top CLK_MOUT_SCLK_SPDIF>,
242 <&cmu_top CLK_DIV_SCLK_AUDIO0>,
243 <&cmu_top CLK_DIV_SCLK_AUDIO1>,
244 <&cmu_top CLK_DIV_SCLK_PCM1>,
245 <&cmu_top CLK_DIV_SCLK_I2S1>;
247 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>,
[all …]
Dexynos850.dtsi240 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
241 <&cmu_top CLK_DOUT_PERI_UART>,
242 <&cmu_top CLK_DOUT_PERI_IP>;
252 clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>;
261 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>;
279 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>,
280 <&cmu_top CLK_DOUT_CORE_CCI>,
281 <&cmu_top CLK_DOUT_CORE_MMC_EMBD>,
282 <&cmu_top CLK_DOUT_CORE_SSS>;
288 cmu_top: clock-controller@120e0000 { label
[all …]
Dexynos5433.dtsi368 cmu_top: clock-controller@10030000 { label
432 <&cmu_top CLK_ACLK_FSYS_200>,
433 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
434 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
435 <&cmu_top CLK_SCLK_MMC2_FSYS>,
436 <&cmu_top CLK_SCLK_MMC1_FSYS>,
437 <&cmu_top CLK_SCLK_MMC0_FSYS>,
438 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
439 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
451 <&cmu_top CLK_ACLK_G2D_266>,
[all …]
Dexynosautov9.dtsi179 <&cmu_top DOUT_CLKCMU_PERIS_BUS>;
190 <&cmu_top DOUT_CLKCMU_PERIC0_BUS>,
191 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
203 <&cmu_top DOUT_CLKCMU_PERIC1_BUS>,
204 <&cmu_top DOUT_CLKCMU_PERIC1_IP>;
216 <&cmu_top DOUT_CLKCMU_FSYS1_BUS>,
217 <&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>,
218 <&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>;
231 <&cmu_top DOUT_CLKCMU_FSYS0_BUS>,
232 <&cmu_top DOUT_CLKCMU_FSYS0_PCIE>;
[all …]
Dexynos850-e850-96.dts130 <&cmu_top CLK_DOUT_HSI_BUS>,
131 <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
132 <&cmu_top CLK_DOUT_HSI_USB20DRD>;
/Linux-v6.6/include/dt-bindings/clock/
Dsamsung,exynosautov9.h12 /* CMU_TOP */
19 /* MUX in CMU_TOP */
68 /* DIV in CMU_TOP */
120 /* GAT in CMU_TOP */
Dexynos7885.h11 /* CMU_TOP */
Dexynos850.h12 /* CMU_TOP */
Dexynos5260-clk.h14 /* List Of Clocks For CMU_TOP */
Dexynos5433.h10 /* CMU_TOP */
/Linux-v6.6/drivers/clk/samsung/
Dclk-exynos7885.c25 /* ---- CMU_TOP ------------------------------------------------------------- */
27 /* Register Offset definitions for CMU_TOP (0x12060000) */
165 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
173 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
184 /* List of parent clocks for Muxes in CMU_TOP: for CMU_FSYS */
352 /* Register CMU_TOP early, as it's a dependency for other early domains */
Dclk-exynos850.c32 /* ---- CMU_TOP ------------------------------------------------------------- */
34 /* Register Offset definitions for CMU_TOP (0x120e0000) */
217 /* List of parent clocks for Muxes in CMU_TOP */
221 /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */
223 /* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */
226 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
237 /* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
240 /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */
248 /* List of parent clocks for Muxes in CMU_TOP: for CMU_IS */
257 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MFCMSCL */
[all …]
Dclk-exynos5250.c269 * CMU_TOP
360 * CMU_TOP
453 * CMU_TOP
611 GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
Dclk-exynosautov9.c30 /* ---- CMU_TOP ------------------------------------------------------------ */
32 /* Register Offset definitions for CMU_TOP (0x1b240000) */
365 /* List of parent clocks for Muxes in CMU_TOP */
965 /* Register CMU_TOP early, as it's a dependency for other early domains */
Dclk-exynos5260.h364 *Registers for CMU_TOP
Dclk-exynos5260.c1402 /* CMU_TOP */
Dclk-exynos5433.c48 * Register offset definitions for CMU_TOP