Lines Matching full:cmu_top
23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
24 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
81 - description: CMU_CORE bus clock (from CMU_TOP)
82 - description: CCI clock (from CMU_TOP)
83 - description: G3D clock (from CMU_TOP)
103 - description: CMU_FSYS bus clock (from CMU_TOP)
104 - description: MMC_CARD clock (from CMU_TOP)
105 - description: MMC_EMBD clock (from CMU_TOP)
106 - description: MMC_SDIO clock (from CMU_TOP)
107 - description: USB30DRD clock (from CMU_TOP)
129 - description: CMU_PERI bus clock (from CMU_TOP)
130 - description: SPI0 clock (from CMU_TOP)
131 - description: SPI1 clock (from CMU_TOP)
132 - description: UART0 clock (from CMU_TOP)
133 - description: UART1 clock (from CMU_TOP)
134 - description: UART2 clock (from CMU_TOP)
135 - description: USI0 clock (from CMU_TOP)
136 - description: USI1 clock (from CMU_TOP)
137 - description: USI2 clock (from CMU_TOP)
172 <&cmu_top CLK_DOUT_PERI_BUS>,
173 <&cmu_top CLK_DOUT_PERI_SPI0>,
174 <&cmu_top CLK_DOUT_PERI_SPI1>,
175 <&cmu_top CLK_DOUT_PERI_UART0>,
176 <&cmu_top CLK_DOUT_PERI_UART1>,
177 <&cmu_top CLK_DOUT_PERI_UART2>,
178 <&cmu_top CLK_DOUT_PERI_USI0>,
179 <&cmu_top CLK_DOUT_PERI_USI1>,
180 <&cmu_top CLK_DOUT_PERI_USI2>;