Home
last modified time | relevance | path

Searched +full:4 +full:- +full:way (Results 1 – 25 of 1052) sorted by relevance

12345678910>>...43

/Linux-v6.1/arch/x86/kernel/cpu/
Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0
6 * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
29 #define LVL_3 4
51 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
52 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
53 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
54 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
55 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
56 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
57 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
[all …]
Dintel.c1 // SPDX-License-Identifier: GPL-2.0
22 #include <asm/intel-family.h>
67 * Processors which have self-snooping capability can handle conflicting
75 switch (c->x86_model) { in check_memory_type_self_snoop_errata()
107 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
109 switch (c->x86_model) { in probe_xeon_phi_r3mwait()
131 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
132 * - https://kb.vmware.com/s/article/52345
133 * - Microcode revisions observed in the wild
134 * - Release note from 20180108 microcode release
[all …]
/Linux-v6.1/arch/arc/mm/
Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
24 * Utility Routine to erase a J-TLB entry
87 * with existing location. This will cause Write CMD to over-write in tlb_entry_insert()
129 * Un-conditionally (without lookup) erase the entire MMU contents
137 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
173 * Flush the entire MM for userland. The fastest way is to move to Next ASID
183 if (atomic_read(&mm->mm_users) == 0) in local_flush_tlb_mm()
187 * - Move to a new ASID, but only if the mm is still wired in in local_flush_tlb_mm()
188 * (Android Binder ended up calling this for vma->mm != tsk->mm, in local_flush_tlb_mm()
[all …]
/Linux-v6.1/arch/xtensa/include/asm/
Dtlbflush.h6 * Copyright (C) 2001 - 2013 Tensilica Inc.
17 #define ITLB_ARF_WAYS 4
18 #define DTLB_ARF_WAYS 4
21 #define DTLB_HIT_BIT 4
27 * - flush_tlb_all() flushes all processes TLB entries
28 * - flush_tlb_mm(mm) flushes the specified mm context TLB entries
29 * - flush_tlb_page(vma, page) flushes a single page
30 * - flush_tlb_range(vma, vmaddr, end) flushes a range of pages
130 static inline void write_dtlb_entry (pte_t entry, int way) in write_dtlb_entry() argument
133 : : "r" (way), "r" (entry) ); in write_dtlb_entry()
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
3 #include "bcm2835-rpi-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a53-pmu";
24 interrupt-parent = <&local_intc>;
[all …]
Dbcm2836.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "bcm2835-common.dtsi"
4 #include "bcm2835-rpi-common.dtsi"
12 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
15 compatible = "brcm,bcm2836-l1-intc";
17 interrupt-controller;
18 #interrupt-cells = <2>;
19 interrupt-parent = <&local_intc>;
23 arm-pmu {
24 compatible = "arm,cortex-a7-pmu";
[all …]
/Linux-v6.1/arch/mips/mm/
Dcerr-sb1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.)
73 printk(" multiple-buserr"); in breakout_errctl()
80 printk(" tag-parity"); in breakout_cerri()
82 printk(" data-parity"); in breakout_cerri()
114 printk(" multi-err"); in breakout_cerrd()
116 printk(" tag-state"); in breakout_cerrd()
118 printk(" tag-address"); in breakout_cerrd()
120 printk(" data-SBE"); in breakout_cerrd()
122 printk(" data-DBE"); in breakout_cerrd()
[all …]
Dc-r4k.c22 #include <linux/dma-map-ops.h> /* for dma_default_coherent */
29 #include <asm/cpu-features.h>
30 #include <asm/cpu-type.h>
38 #include <asm/mips-cps.h>
43 * R4K_HIT - Virtual user or kernel address based cache operations. The
46 * R4K_INDEX - Index based cache operations.
53 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
68 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */ in r4k_op_needs_ipi()
74 * be needed, but only if there are foreign CPUs (non-siblings with in r4k_op_needs_ipi()
294 unsigned long indexmask = current_cpu_data.icache.waysize - 1; in tx49_blast_icache32_page_indexed()
[all …]
/Linux-v6.1/arch/powerpc/mm/nohash/
Dtlb_low.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low-level functions for performing various
7 * This file implements the following functions for all no-hash
11 * - tlbil_va
12 * - tlbil_pid
13 * - tlbil_all
14 * - tlbivax_bcast
18 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
29 #include <asm/asm-offsets.h>
32 #include <asm/asm-compat.h>
[all …]
/Linux-v6.1/arch/powerpc/platforms/powernv/
Dsubcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
30 * A core can be in one of three states, unsplit, 2-way split, and 4-way split.
35 * ------------|------------------
37 * 2-way split | 2
38 * 4-way split | 4
44 * ----------------------------
46 * ----------------------------
47 * Thread | 0 1 2 3 4 5 6 7 |
48 * ----------------------------
50 * 2-way split:
[all …]
/Linux-v6.1/arch/openrisc/include/asm/
Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
31 #define SPRGROUP_IC (4 << MAX_SPRS_PER_GRP_BITS)
45 #define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) argument
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) argument
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) argument
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) argument
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) argument
[all …]
/Linux-v6.1/arch/x86/crypto/
Dblowfish-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 .file "blowfish-x86_64-asm.S"
16 #define s0 ((16 + 2) * 4)
17 #define s1 ((16 + 2 + (1 * 256)) * 4)
18 #define s2 ((16 + 2 + (2 * 256)) * 4)
19 #define s3 ((16 + 2 + (3 * 256)) * 4)
58 * 1-way blowfish
65 movl s0(CTX,RT0,4), RT0d; \
66 addl s1(CTX,RT1,4), RT0d; \
70 xorl s2(CTX,RT1,4), RT0d; \
[all …]
Dtwofish_glue_3way.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Glue Code for 3-way parallel assembler optimized version of Twofish
24 return twofish_setkey(&tfm->base, key, keylen); in twofish_setkey_skcipher()
47 ECB_WALK_START(req, TF_BLOCK_SIZE, -1); in ecb_encrypt()
55 ECB_WALK_START(req, TF_BLOCK_SIZE, -1); in ecb_decrypt()
63 CBC_WALK_START(req, TF_BLOCK_SIZE, -1); in cbc_encrypt()
70 CBC_WALK_START(req, TF_BLOCK_SIZE, -1); in cbc_decrypt()
79 .base.cra_driver_name = "ecb-twofish-3way",
91 .base.cra_driver_name = "cbc-twofish-3way",
115 * On Atom, twofish-3way is slower than original assembler in is_blacklisted_cpu()
[all …]
/Linux-v6.1/arch/mips/kernel/
Dbmips_5xxx_init.S7 * Copyright (C) 2011-2012 by Broadcom Corporation
34 addiu t1, t1, -1 ; \
74 #define CP0_BRCM_MODE_ClkRATIO_MASK (7 << 4)
85 #define BRCM_ZSC_RBUS_ADDR_MAPPING_REG0 4 << 3
112 * Description: compute the I-cache size and I-cache line size
126 * Determine sets per way: IS
128 * This field contains the number of sets (i.e., indices) per way of
131 * vi) 0x5 - 0x7: Reserved.
137 /* sets per way = (64<<IS) */
146 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
[all …]
/Linux-v6.1/Documentation/userspace-api/media/v4l/
Dyuv-formats.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _yuv-formats:
12 *color difference* signals, this way the green component can be
16 color in a way compatible with existing receivers a new signal carrier
29 direction are possible, common factors are 1 (no subsampling), 2 and 4, with
33 - `4:4:4`: No subsampling
34 - `4:2:2`: Horizontal subsampling by 2, no vertical subsampling
35 - `4:2:0`: Horizontal subsampling by 2, vertical subsampling by 2
36 - `4:1:1`: Horizontal subsampling by 4, no vertical subsampling
37 - `4:1:0`: Horizontal subsampling by 4, vertical subsampling by 4
[all …]
/Linux-v6.1/arch/sh/mm/
Dcache-sh2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/sh/mm/cache-sh2.c
23 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_wback_region()
24 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2__flush_wback_region()
25 & ~(L1_CACHE_BYTES-1); in sh2__flush_wback_region()
28 int way; in sh2__flush_wback_region() local
29 for (way = 0; way < 4; way++) { in sh2__flush_wback_region()
30 unsigned long data = __raw_readl(addr | (way << 12)); in sh2__flush_wback_region()
33 __raw_writel(data, addr | (way << 12)); in sh2__flush_wback_region()
44 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_purge_region()
[all …]
/Linux-v6.1/arch/arm/mm/
Dcache-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v7.S
15 #include <asm/hardware/cache-b15-rac.h>
17 #include "proc-macros.S"
49 mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...]
51 moveq r1, #1 @ r1 needs value > 0 even if only 1 way
54 add r2, r2, #4 @ SetShift
62 subs r0, r0, #1 @ Set--
64 subs r3, r3, r1 @ Way--
66 mrc p15, 1, r0, c0, c0, 0 @ re-read cache geometry from CCSIDR
[all …]
Dcache-v7m.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v7m.S
5 * Based on linux/arch/arm/mm/cache-v7.S
19 #include "proc-macros.S"
48 * dcisw: Invalidate data cache by set/way
55 * dccisw: Clean and invalidate data cache by set/way
129 and r3, r1, r0, lsr #3 @ NumWays - 1
133 add r0, r0, #4 @ SetShift
137 1: sub r2, r2, #1 @ NumSets--
139 2: subs r3, r3, #1 @ Temp--
[all …]
Dproc-arm940.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
12 #include <asm/pgtable-hwdef.h>
14 #include "proc-macros.S"
16 /* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
18 #define CACHE_DSEGMENTS 4
37 bic r0, r0, #0x00001000 @ i-cache
38 bic r0, r0, #0x00000004 @ d-cache
52 mcr p15, 0, ip, c7, c10, 4 @ drain WB
55 bic ip, ip, #0x00001000 @ i-cache
[all …]
/Linux-v6.1/arch/mips/include/asm/octeon/
Dcvmx-l2c.h7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
44 #define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
52 /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
74 CVMX_L2C_EVENT_DATA_HIT = 4,
133 CVMX_L2C_TAD_EVENT_TAG_VICTIM = 4,
183 * Return the L2 Cache way partitioning for a given core.
189 * -1 on error
199 * a way, while a 1 bit blocks the core from evicting any
[all …]
/Linux-v6.1/Documentation/ia64/
Defirtc.rst13 the IA-64 platform.
18 EFI provides 4 calls one can make once the OS is booted: GetTime(),
28 portable way, the CMOS clock. A program like /sbin/hwclock uses such a clock
31 Because we wanted to minimize the impact on existing user-level apps using
38 EFI uses a slightly different way of representing the time, noticeably
39 the reference date is different. Year is the using the full 4-digit format.
41 expose this new way of representing time. Instead we use something very
43 One of the reasons for doing it this way is to allow for EFI to still evolve
48 ioctl()s. The other is read-only via the /proc filesystem.
94 # /sbin/hwclock --show
[all …]
/Linux-v6.1/Documentation/admin-guide/
Ddevices.txt1 0 Unnamed devices (e.g. non-device mounts)
7 2 = /dev/kmem OBSOLETE - replaced by /proc/kcore
9 4 = /dev/port I/O port access
11 6 = /dev/core OBSOLETE - replaced by /proc/kcore
18 12 = /dev/oldmem OBSOLETE - replaced by /proc/vmcore
31 2 char Pseudo-TTY masters
37 Pseudo-tty's are named as follows:
40 the 1st through 16th series of 16 pseudo-ttys each, and
44 These are the old-style (BSD) PTY devices; Unix98
61 4 = /dev/fd?d360 5.25" 360K in a 360K drive(1)
[all …]
/Linux-v6.1/arch/sparc/mm/
Dleon_mm.c1 // SPDX-License-Identifier: GPL-2.0
32 return (retval & SRMMU_CTX_PMASK) << 4; in leon_get_ctable_ptr()
67 printk(KERN_INFO "swprobe: --- ctx (%x) ---\n", ctx); in leon_swprobe()
69 pgd = LEON_BYPASS_LOAD_PA(ctxtbl + (ctx * 4)); in leon_swprobe()
86 printk(KERN_INFO "swprobe: --- pgd (%x) ---\n", pgd); in leon_swprobe()
88 ptr = (pgd & SRMMU_PTD_PMASK) << 4; in leon_swprobe()
89 ptr += ((((vaddr) >> LEON_PGD_SH) & LEON_PGD_M) * 4); in leon_swprobe()
109 printk(KERN_INFO "swprobe: --- pmd (%x) ---\n", pmd); in leon_swprobe()
111 ptr = (pmd & SRMMU_PTD_PMASK) << 4; in leon_swprobe()
112 ptr += (((vaddr >> LEON_PMD_SH) & LEON_PMD_M) * 4); in leon_swprobe()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/mux/
Dmux-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
20 space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
21 0-7 for an 8-way multiplexer, etc.
25 --------------------
28 specifier using the '#mux-control-cells' or '#mux-state-cells' property.
29 The value of '#mux-state-cells' will always be one greater than the value
[all …]
/Linux-v6.1/Documentation/networking/
Dnexthop-group-resilient.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Resilient Next-hop Groups
7 Resilient groups are a type of next-hop group that is aimed at minimizing
12 the legacy multipath next-hop group, which uses the hash-threshold
15 To select a next hop, hash-threshold algorithm first assigns a range of
22 +-------+-------+-------+-------+-------+
23 | 1 | 2 | 3 | 4 | 5 |
24 +-------+-+-----+---+---+-----+-+-------+
25 | 1 | 2 | 4 | 5 |
26 +---------+---------+---------+---------+
[all …]

12345678910>>...43