Lines Matching +full:4 +full:- +full:way
22 #include <linux/dma-map-ops.h> /* for dma_default_coherent */
29 #include <asm/cpu-features.h>
30 #include <asm/cpu-type.h>
38 #include <asm/mips-cps.h>
43 * R4K_HIT - Virtual user or kernel address based cache operations. The
46 * R4K_INDEX - Index based cache operations.
53 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
68 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */ in r4k_op_needs_ipi()
74 * be needed, but only if there are foreign CPUs (non-siblings with in r4k_op_needs_ipi()
294 unsigned long indexmask = current_cpu_data.icache.waysize - 1; in tx49_blast_icache32_page_indexed()
499 * is not cached in the S-cache, we know it also won't be in local_r4k___flush_cache_all()
528 * has_valid_asid() - Determine if an mm already has an ASID.
538 * Must be called in non-preemptive context.
584 int exec = vma->vm_flags & VM_EXEC; in local_r4k_flush_cache_range()
586 if (!has_valid_asid(vma->vm_mm, R4K_INDEX)) in local_r4k_flush_cache_range()
604 int exec = vma->vm_flags & VM_EXEC; in r4k_flush_cache_range()
620 * R4000SC and R4400SC indexed S-cache ops also invalidate primary in local_r4k_flush_cache_mm()
651 struct vm_area_struct *vma = fcp_args->vma; in local_r4k_flush_cache_page()
652 unsigned long addr = fcp_args->addr; in local_r4k_flush_cache_page()
653 struct page *page = pfn_to_page(fcp_args->pfn); in local_r4k_flush_cache_page()
654 int exec = vma->vm_flags & VM_EXEC; in local_r4k_flush_cache_page()
655 struct mm_struct *mm = vma->vm_mm; in local_r4k_flush_cache_page()
679 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) in local_r4k_flush_cache_page()
703 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { in local_r4k_flush_cache_page()
758 (type & R4K_INDEX && end - start >= dcache_size)) { in __local_r4k_flush_icache_range()
770 (type & R4K_INDEX && end - start > icache_size)) in __local_r4k_flush_icache_range()
803 unsigned long start = fir_args->start; in local_r4k_flush_icache_range_ipi()
804 unsigned long end = fir_args->end; in local_r4k_flush_icache_range_ipi()
805 unsigned int type = fir_args->type; in local_r4k_flush_icache_range_ipi()
806 bool user = fir_args->user; in local_r4k_flush_icache_range_ipi()
829 * If address-based cache ops don't require an SMP call, then in __r4k_flush_icache_range()
832 size = end - start; in __r4k_flush_icache_range()
883 * If we would need IPI to perform an INDEX-type operation, then in r4k_dma_cache_wback_inv()
884 * we have to use the HIT-type alternative as IPI cannot be used in r4k_dma_cache_wback_inv()
904 addr0 &= ~(linesz - 1); in prefetch_cache_inv()
905 addr1 = (addr0 + size - 1) & ~(linesz - 1); in prefetch_cache_inv()
919 addr1 -= linesz; in prefetch_cache_inv()
985 * S-caches or T-caches. in local_r4k_flush_kernel_vmap_range_index()
993 unsigned long vaddr = vmra->vaddr; in local_r4k_flush_kernel_vmap_range()
994 int size = vmra->size; in local_r4k_flush_kernel_vmap_range()
998 * S-caches or T-caches. in local_r4k_flush_kernel_vmap_range()
1053 unsigned int imp = c->processor_id & PRID_IMP_MASK; in alias_74k_erratum()
1054 unsigned int rev = c->processor_id & PRID_REV_MASK; in alias_74k_erratum()
1064 * address hit during a D-cache look-up. in alias_74k_erratum()
1068 if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) in alias_74k_erratum()
1070 if (rev == PRID_REV_ENCODE_332(2, 4, 0)) in alias_74k_erratum()
1098 static char *way_string[] = { NULL, "direct mapped", "2-way",
1099 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
1100 "9-way", "10-way", "11-way", "12-way",
1101 "13-way", "14-way", "15-way", "16-way",
1114 case CPU_R4600: /* QED style two way caches? */ in probe_pcache()
1119 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1120 c->icache.ways = 2; in probe_pcache()
1121 c->icache.waybit = __ffs(icache_size/2); in probe_pcache()
1124 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1125 c->dcache.ways = 2; in probe_pcache()
1126 c->dcache.waybit= __ffs(dcache_size/2); in probe_pcache()
1128 c->options |= MIPS_CPU_CACHE_CDEX_P; in probe_pcache()
1133 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1134 c->icache.ways = 2; in probe_pcache()
1135 c->icache.waybit= 0; in probe_pcache()
1138 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1139 c->dcache.ways = 2; in probe_pcache()
1140 c->dcache.waybit = 0; in probe_pcache()
1142 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; in probe_pcache()
1147 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1148 c->icache.ways = 4; in probe_pcache()
1149 c->icache.waybit= 0; in probe_pcache()
1152 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1153 c->dcache.ways = 4; in probe_pcache()
1154 c->dcache.waybit = 0; in probe_pcache()
1156 c->options |= MIPS_CPU_CACHE_CDEX_P; in probe_pcache()
1157 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1168 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1169 c->icache.ways = 1; in probe_pcache()
1170 c->icache.waybit = 0; /* doesn't matter */ in probe_pcache()
1173 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1174 c->dcache.ways = 1; in probe_pcache()
1175 c->dcache.waybit = 0; /* does not matter */ in probe_pcache()
1177 c->options |= MIPS_CPU_CACHE_CDEX_P; in probe_pcache()
1185 c->icache.linesz = 64; in probe_pcache()
1186 c->icache.ways = 2; in probe_pcache()
1187 c->icache.waybit = 0; in probe_pcache()
1190 c->dcache.linesz = 32; in probe_pcache()
1191 c->dcache.ways = 2; in probe_pcache()
1192 c->dcache.waybit = 0; in probe_pcache()
1194 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1201 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1202 c->icache.ways = 4; in probe_pcache()
1203 c->icache.waybit = __ffs(icache_size / c->icache.ways); in probe_pcache()
1206 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1207 c->dcache.ways = 4; in probe_pcache()
1208 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); in probe_pcache()
1210 c->options |= MIPS_CPU_CACHE_CDEX_P; in probe_pcache()
1211 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1216 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1218 c->icache.ways = 4; in probe_pcache()
1220 c->icache.ways = 2; in probe_pcache()
1221 c->icache.waybit = 0; in probe_pcache()
1224 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1226 c->dcache.ways = 4; in probe_pcache()
1228 c->dcache.ways = 2; in probe_pcache()
1229 c->dcache.waybit = 0; in probe_pcache()
1236 c->icache.linesz = 2 << lsize; in probe_pcache()
1238 c->icache.linesz = 0; in probe_pcache()
1239 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_pcache()
1240 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_pcache()
1241 icache_size = c->icache.sets * in probe_pcache()
1242 c->icache.ways * in probe_pcache()
1243 c->icache.linesz; in probe_pcache()
1244 c->icache.waybit = 0; in probe_pcache()
1248 c->dcache.linesz = 2 << lsize; in probe_pcache()
1250 c->dcache.linesz = 0; in probe_pcache()
1251 c->dcache.sets = 64 << ((config1 >> 13) & 7); in probe_pcache()
1252 c->dcache.ways = 1 + ((config1 >> 7) & 7); in probe_pcache()
1253 dcache_size = c->dcache.sets * in probe_pcache()
1254 c->dcache.ways * in probe_pcache()
1255 c->dcache.linesz; in probe_pcache()
1256 c->dcache.waybit = 0; in probe_pcache()
1257 if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >= in probe_pcache()
1259 (c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R) in probe_pcache()
1260 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1265 c->icache.linesz = 128; in probe_pcache()
1266 c->icache.sets = 16; in probe_pcache()
1267 c->icache.ways = 8; in probe_pcache()
1268 c->icache.flags |= MIPS_CACHE_VTAG; in probe_pcache()
1269 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; in probe_pcache()
1271 c->dcache.linesz = 128; in probe_pcache()
1272 c->dcache.ways = 8; in probe_pcache()
1273 c->dcache.sets = 8; in probe_pcache()
1274 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_pcache()
1275 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1280 panic("Don't know how to probe P-caches on this cpu."); in probe_pcache()
1284 * So let's probe the I-cache ... in probe_pcache()
1294 c->icache.linesz = lsize ? 2 << lsize : 0; in probe_pcache()
1296 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); in probe_pcache()
1297 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_pcache()
1299 icache_size = c->icache.sets * in probe_pcache()
1300 c->icache.ways * in probe_pcache()
1301 c->icache.linesz; in probe_pcache()
1302 c->icache.waybit = __ffs(icache_size/c->icache.ways); in probe_pcache()
1305 c->icache.flags |= MIPS_CACHE_VTAG; in probe_pcache()
1310 c->dcache.flags = 0; in probe_pcache()
1318 c->dcache.linesz = lsize ? 2 << lsize : 0; in probe_pcache()
1320 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); in probe_pcache()
1321 c->dcache.ways = 1 + ((config1 >> 7) & 7); in probe_pcache()
1323 dcache_size = c->dcache.sets * in probe_pcache()
1324 c->dcache.ways * in probe_pcache()
1325 c->dcache.linesz; in probe_pcache()
1326 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); in probe_pcache()
1328 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1342 !(config & CONF_SC) && c->icache.linesz != 16 && in probe_pcache()
1347 c->icache.waysize = icache_size / c->icache.ways; in probe_pcache()
1348 c->dcache.waysize = dcache_size / c->dcache.ways; in probe_pcache()
1350 c->icache.sets = c->icache.linesz ? in probe_pcache()
1351 icache_size / (c->icache.linesz * c->icache.ways) : 0; in probe_pcache()
1352 c->dcache.sets = c->dcache.linesz ? in probe_pcache()
1353 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; in probe_pcache()
1356 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way in probe_pcache()
1368 c->dcache.flags |= MIPS_CACHE_PINDEX; in probe_pcache()
1394 (c->icache.waysize > PAGE_SIZE)) in probe_pcache()
1395 c->icache.flags |= MIPS_CACHE_ALIASES; in probe_pcache()
1401 c->dcache.flags |= MIPS_CACHE_PINDEX; in probe_pcache()
1406 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE) in probe_pcache()
1407 c->dcache.flags |= MIPS_CACHE_ALIASES; in probe_pcache()
1411 if (c->dcache.flags & MIPS_CACHE_PINDEX) in probe_pcache()
1412 c->dcache.flags &= ~MIPS_CACHE_ALIASES; in probe_pcache()
1420 c->icache.flags |= MIPS_IC_SNOOPS_REMOTE; in probe_pcache()
1428 c->icache.flags |= MIPS_CACHE_VTAG; in probe_pcache()
1434 c->icache.flags |= MIPS_CACHE_IC_F_DC; in probe_pcache()
1438 c->icache.flags |= MIPS_CACHE_IC_F_DC; in probe_pcache()
1440 c->dcache.flags &= ~MIPS_CACHE_ALIASES; in probe_pcache()
1445 * LOONGSON2 has 4 way icache, but when using indexed cache op, in probe_pcache()
1446 * one op will act on all 4 ways in probe_pcache()
1448 c->icache.ways = 1; in probe_pcache()
1453 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", in probe_pcache()
1454 way_string[c->icache.ways], c->icache.linesz); in probe_pcache()
1457 dcache_size >> 10, way_string[c->dcache.ways], in probe_pcache()
1458 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", in probe_pcache()
1459 (c->dcache.flags & MIPS_CACHE_ALIASES) ? in probe_pcache()
1461 c->dcache.linesz); in probe_pcache()
1474 c->vcache.linesz = 2 << lsize; in probe_vcache()
1476 c->vcache.linesz = lsize; in probe_vcache()
1478 c->vcache.sets = 64 << ((config2 >> 24) & 15); in probe_vcache()
1479 c->vcache.ways = 1 + ((config2 >> 16) & 15); in probe_vcache()
1481 vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz; in probe_vcache()
1483 c->vcache.waybit = 0; in probe_vcache()
1484 c->vcache.waysize = vcache_size / c->vcache.ways; in probe_vcache()
1487 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz); in probe_vcache()
1506 begin &= ~((4 * 1024 * 1024) - 1); in probe_scache()
1507 end = begin + (4 * 1024 * 1024); in probe_scache()
1515 /* Fill each size-multiple cache line with a valid tag. */ in probe_scache()
1541 addr -= begin; in probe_scache()
1544 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); in probe_scache()
1545 c->scache.ways = 1; in probe_scache()
1546 c->scache.waybit = 0; /* does not matter */ in probe_scache()
1556 c->scache.linesz = 32; in loongson2_sc_init()
1557 c->scache.ways = 4; in loongson2_sc_init()
1558 c->scache.waybit = 0; in loongson2_sc_init()
1559 c->scache.waysize = scache_size / (c->scache.ways); in loongson2_sc_init()
1560 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); in loongson2_sc_init()
1562 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); in loongson2_sc_init()
1564 c->options |= MIPS_CPU_INCLUSIVE_CACHES; in loongson2_sc_init()
1573 lsize = (config2 >> 4) & 15; in loongson3_sc_init()
1575 c->scache.linesz = 2 << lsize; in loongson3_sc_init()
1577 c->scache.linesz = 0; in loongson3_sc_init()
1578 c->scache.sets = 64 << ((config2 >> 8) & 15); in loongson3_sc_init()
1579 c->scache.ways = 1 + (config2 & 15); in loongson3_sc_init()
1581 /* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */ in loongson3_sc_init()
1582 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R) in loongson3_sc_init()
1583 c->scache.sets *= 2; in loongson3_sc_init()
1585 c->scache.sets *= 4; in loongson3_sc_init()
1587 scache_size = c->scache.sets * c->scache.ways * c->scache.linesz; in loongson3_sc_init()
1589 c->scache.waybit = 0; in loongson3_sc_init()
1590 c->scache.waysize = scache_size / c->scache.ways; in loongson3_sc_init()
1592 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); in loongson3_sc_init()
1594 c->options |= MIPS_CPU_INCLUSIVE_CACHES; in loongson3_sc_init()
1610 * processors don't have a S-cache that would be relevant to the in setup_scache()
1620 c->options |= MIPS_CPU_CACHE_CDEX_S; in setup_scache()
1628 c->scache.linesz = 64 << ((config >> 13) & 1); in setup_scache()
1629 c->scache.ways = 2; in setup_scache()
1630 c->scache.waybit= 0; in setup_scache()
1660 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | in setup_scache()
1666 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; in setup_scache()
1669 way_string[c->scache.ways], c->scache.linesz); in setup_scache()
1672 c->options |= MIPS_CPU_INCLUSIVE_CACHES; in setup_scache()
1676 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) in setup_scache()
1688 c->scache.waysize = scache_size / c->scache.ways; in setup_scache()
1690 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); in setup_scache()
1693 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); in setup_scache()
1695 c->options |= MIPS_CPU_INCLUSIVE_CACHES; in setup_scache()
1745 static int cca = -1;
1783 * the write-only co_config.od bit and set it back to one on: in coherency_setup()
1843 if (c->dcache.linesz && cpu_has_dc_aliases) in r4k_cache_init()
1845 c->dcache.sets * c->dcache.linesz - 1, in r4k_cache_init()
1846 PAGE_SIZE - 1); in r4k_cache_init()
1848 shm_align_mask = PAGE_SIZE-1; in r4k_cache_init()
1895 * Per-CPU overrides in r4k_cache_init()
1905 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT) in r4k_cache_init()
1921 /* Loongson-3 maintains cache coherency by hardware */ in r4k_cache_init()