Lines Matching +full:4 +full:- +full:way
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v7.S
15 #include <asm/hardware/cache-b15-rac.h>
17 #include "proc-macros.S"
49 mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...]
51 moveq r1, #1 @ r1 needs value > 0 even if only 1 way
54 add r2, r2, #4 @ SetShift
62 subs r0, r0, #1 @ Set--
64 subs r3, r3, r1 @ Way--
66 mrc p15, 1, r0, c0, c0, 0 @ re-read cache geometry from CCSIDR
76 * Flush the whole I-cache.
79 * r0 - set to 0
83 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
91 * Flush the D-cache up to the Level of Unification Inner Shareable
93 * Corrupted registers: r0-r6, r9-r10
106 movw r1, #:lower16:(0x410fc090 >> 4) @ ID of ARM Cortex A9 r0p?
107 movt r1, #:upper16:(0x410fc090 >> 4)
108 teq r1, r2, lsr #4 @ test for errata affected core and if so...
118 * Flush the whole D-cache.
120 * Corrupted registers: r0-r6, r9-r10
122 * - mm - mm_struct describing address space
137 blt skip @ skip if no cache, or just i-cache
148 add r2, r2, #4 @ add 4 (line length offset)
150 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
151 clz r5, r4 @ find bit position of way size increment
161 orr r5, r5, r4 @ factor way number into r5
163 mcr p15, 0, r5, c7, c14, 2 @ clean & invalidate by set/way
166 subs r4, r4, r6 @ decrement the way
188 * working outwards from L1 cache. This is done using Set/Way based cache
195 stmfd sp!, {r4-r6, r9-r10, lr}
198 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
200 ldmfd sp!, {r4-r6, r9-r10, lr}
208 * Invalidate the I-cache to the point of unification.
211 stmfd sp!, {r4-r6, r9-r10, lr}
214 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
216 ldmfd sp!, {r4-r6, r9-r10, lr}
225 * - mm - mm_struct describing address space
235 * - start - start address (may not be aligned)
236 * - end - end address (exclusive, may not be aligned)
237 * - flags - vm_area_struct flags describing address space
240 * - we have a VIPT cache.
254 * - start - virtual start address of region
255 * - end - virtual end address of region
258 * - the Icache does not read data from the write buffer
270 * - start - virtual start address of region
271 * - end - virtual end address of region
274 * - the Icache does not read data from the write buffer
313 * isn't mapped, fail with -EFAULT.
319 mov r0, #-EFAULT
331 * - addr - kernel address
332 * - size - region size
359 * - start - virtual start address of region
360 * - end - virtual end address of region
389 * - start - virtual start address of region
390 * - end - virtual end address of region
411 * - start - virtual start address of region
412 * - end - virtual end address of region
433 * - start - kernel virtual start address
434 * - size - size of region
435 * - dir - DMA direction
446 * - start - kernel virtual start address
447 * - size - size of region
448 * - dir - DMA direction
459 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
462 /* The Broadcom Brahma-B15 read-ahead cache requires some modifications