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/Linux-v6.1/drivers/clk/samsung/
Dclk-s3c2410.c62 { .val = 1, .div = 2 },
63 { .val = 2, .div = 4 },
123 PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
124 PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
125 PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
126 PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
127 PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
129 PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
130 PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1),
131 PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1),
[all …]
Dclk-exynos3250.c99 #define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
228 FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
229 FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
344 DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
455 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
497 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
508 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
536 GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
547 GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
564 GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
[all …]
/Linux-v6.1/drivers/clk/spear/
Dspear1340_clock.c32 #define SPEAR1340_GEN_SYNT_CLK_MASK 2
34 #define SPEAR1340_PLL_CLK_MASK 2
57 #define SPEAR1340_UART_CLK_MASK 2
60 #define SPEAR1340_CLCD_CLK_MASK 2
61 #define SPEAR1340_CLCD_CLK_SHIFT 2
67 #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2
68 #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2
85 #define SPEAR1340_I2S_REF_SHIFT 2
86 #define SPEAR1340_I2S_SRC_CLK_MASK 2
128 #define SPEAR1340_SYSRAM1_CLK_ENB 2
[all …]
Dspear1310_clock.c24 #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2
26 #define SPEAR1310_RAS_SYNT_CLK_MASK 2
28 #define SPEAR1310_PLL_CLK_MASK 2
52 #define SPEAR1310_UART_CLK_SYNT_VAL 2
53 #define SPEAR1310_UART_CLK_MASK 2
58 #define SPEAR1310_CLCD_CLK_MASK 2
59 #define SPEAR1310_CLCD_CLK_SHIFT 2
68 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2
85 #define SPEAR1310_I2S_REF_SHIFT 2
86 #define SPEAR1310_I2S_SRC_CLK_MASK 2
[all …]
/Linux-v6.1/arch/arm/mach-omap2/
Dopp2xxx.h70 #define R1_CLKSEL_L4 (2 << 5)
75 #define R1_CLKSEL_MPU (2 << 0)
77 #define R1_CLKSEL_DSP (2 << 0)
78 #define R1_CLKSEL_DSP_IF (2 << 5)
80 #define R1_CLKSEL_GFX (2 << 0)
85 /* 2430-Ratio Config 2 */
87 #define R2_CLKSEL_L4 (2 << 5)
88 #define R2_CLKSEL_USB (2 << 25)
92 #define R2_CLKSEL_MPU (2 << 0)
94 #define R2_CLKSEL_DSP (2 << 0)
[all …]
/Linux-v6.1/drivers/clk/mvebu/
Dmv98dx3236.c25 * 0 = 400 MHz 400 MHz 800 MHz
26 * 2 = 667 MHz 667 MHz 2000 MHz
27 * 3 = 800 MHz 800 MHz 1600 MHz
34 * 1 = 667 MHz 667 MHz 2000 MHz
35 * 2 = 400 MHz 400 MHz 400 MHz
36 * 3 = 800 MHz 800 MHz 800 MHz
37 * 5 = 800 MHz 400 MHz 800 MHz
46 /* Tclk = 200MHz, no SaR dependency */ in mv98dx3236_get_tclk_freq()
97 static const int __initconst mv98dx3236_cpu_mpll_ratios[8][2] = {
102 static const int __initconst mv98dx3236_cpu_ddr_ratios[8][2] = {
[all …]
Ddove.c26 * 5 = 1000 MHz
27 * 6 = 933 MHz
28 * 7 = 933 MHz
29 * 8 = 800 MHz
30 * 9 = 800 MHz
31 * 10 = 800 MHz
32 * 11 = 1067 MHz
33 * 12 = 667 MHz
34 * 13 = 533 MHz
35 * 14 = 400 MHz
[all …]
Darmada-375.c29 * 6 = 400 MHz 400 MHz 200 MHz
30 * 15 = 600 MHz 600 MHz 300 MHz
31 * 21 = 800 MHz 534 MHz 400 MHz
32 * 25 = 1000 MHz 500 MHz 500 MHz
36 * 0 = 166 MHz
37 * 1 = 200 MHz
92 static const int armada_375_cpu_l2_ratios[32][2] __initconst = {
94 {0, 1}, {0, 1}, {1, 2}, {0, 1},
96 {0, 1}, {0, 1}, {0, 1}, {1, 2},
98 {0, 1}, {1, 2}, {0, 1}, {0, 1},
[all …]
Dkirkwood.c28 * 4 = 600 MHz
29 * 6 = 800 MHz
30 * 7 = 1000 MHz
31 * 9 = 1200 MHz
32 * 12 = 1500 MHz
33 * 13 = 1600 MHz
34 * 14 = 1800 MHz
35 * 15 = 2000 MHz
39 * 1 = (1/2) * CPU
45 * 2 = (1/2) * CPU
[all …]
/Linux-v6.1/drivers/scsi/qla2xxx/
Dqla_devtbl.h7 static char *qla2x00_model_name[QLA_MODEL_NAMES*2] = {
8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
11 "QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
12 "QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
13 "QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
16 "QCP2332", "Sun cPCI to 2Gb FC, Dual Channel", /* 0x108 */
[all …]
/Linux-v6.1/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
16 # 12 chars 2 lines
18 # 2 chars 10 lines
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
[all …]
/Linux-v6.1/drivers/clk/uniphier/
Dclk-uniphier-sys.c13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
33 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
43 UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
78 UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
94 UNIPHIER_LD4_SYS_CLK_NAND(2),
[all …]
/Linux-v6.1/drivers/media/usb/dvb-usb-v2/
Daf9035.h58 u8 af9033_i2c_addr[2];
60 struct af9033_config af9033_config[2];
65 struct platform_device *platform_device_tuner[2];
81 16384000, /* 16.38 MHz */
82 20480000, /* 20.48 MHz */
83 36000000, /* 36.00 MHz */
84 30000000, /* 30.00 MHz */
85 26000000, /* 26.00 MHz */
86 28000000, /* 28.00 MHz */
87 32000000, /* 32.00 MHz */
[all …]
/Linux-v6.1/drivers/media/tuners/
Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
30 0f 2c ?
57 2a 13 ?
58 2b 01 ?
59 2c ea ?
60 2d 00 ?
61 2e 00 ? not used?
[all …]
/Linux-v6.1/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dphy_shim.h28 #define RADAR_TYPE_ETSI_2 2 /* ETSI 2 Radar type */
34 #define RADAR_TYPE_STG2 8 /* staggered-2 radar */
49 #define ANTSEL_2x4 1 /* 2x4 boardlevel selection available */
50 #define ANTSEL_2x3 2 /* 2x3 CB2 boardlevel selection available */
55 #define ANT_RX_DIV_START_1 2 /* Choose starting with 1 */
60 #define WL_ANT_RX_MAX 2 /* max 2 receive antennas */
63 #define WL_ANT_IDX_2 1 /* antenna index 2 */
68 #define BRCMS_N_PREAMBLE_GF_BRCM 2
80 /* Index for first 20MHz OFDM SISO rate */
82 /* Index for first 20MHz OFDM CDD rate */
[all …]
/Linux-v6.1/drivers/net/wireless/ti/wl12xx/
Dwl12xx.h50 #define WL12XX_NUM_MAC_ADDRESSES 2
73 WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */
74 WL12XX_REFCLOCK_26 = 1, /* 26 MHz */
75 WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */
76 WL12XX_REFCLOCK_52 = 3, /* 52 MHz */
77 WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
78 WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
83 WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */
84 WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */
85 WL12XX_TCXOCLOCK_38_4 = 2, /* 38.4MHz */
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu11_driver_if_vangogh.h45 uint16_t Freq; // in MHz
50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
57 uint8_t Padding[2];
124 //Freq in MHz
125 //Voltage in milli volts with 2 fractional bits
150 uint8_t spare[2];
157 #define THROTTLER_STATUS_BIT_SPPT 2
168 uint16_t GfxclkFrequency; //[MHz]
169 uint16_t SocclkFrequency; //[MHz]
[all …]
Dsmu11_driver_if_sienna_cichlid.h35 #define NUM_SMNCLK_DPM_LEVELS 2
37 #define NUM_MP0CLK_DPM_LEVELS 2
46 #define NUM_MP1CLK_DPM_LEVELS 2
47 #define NUM_LINK_LEVELS 2
49 #define NUM_XGMI_LEVELS 2
72 #define PPSMC_GeminiModeSlave 2 //Slave GPU on a Gemini board
78 #define FEATURE_DPM_GFX_GPO_BIT 2
197 #define THROTTLER_TEMP_HOTSPOT_BIT 2
221 #define FW_DSTATE_G6_PHY_VDDCI_OFF_BIT 2
264 #define LED_DISPLAY_ERROR_BIT 2
[all …]
Dsmu13_driver_if_yellow_carp.h45 uint16_t Freq; // in MHz
50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
57 uint8_t Padding[2];
119 //Freq in MHz
120 //Voltage in milli volts with 2 fractional bits
146 #define THROTTLER_STATUS_BIT_SPPT 2
159 uint16_t GfxclkFrequency; //[MHz]
160 uint16_t SocclkFrequency; //[MHz]
161 uint16_t VclkFrequency; //[MHz]
[all …]
Dsmu12_driver_if.h46 uint16_t Freq; // in MHz
51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
52 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
58 uint8_t Padding[2];
112 uint32_t Freq; // In MHz
113 uint32_t Vol; // Millivolts with 2 fractional bits
130 uint8_t spare[2];
159 #define THROTTLER_STATUS_BIT_SPPT 2
172 uint16_t ClockFrequency[CLOCK_COUNT]; //[MHz]
174 uint16_t AverageGfxclkFrequency; //[MHz]
[all …]
/Linux-v6.1/arch/m68k/include/uapi/asm/
Dbootinfo-hp300.h25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
32 #define HP_375 7 /* 50MHz 68030+32K external cache */
33 #define HP_380 8 /* 25MHz 68040 */
34 #define HP_385 9 /* 33MHz 68040 */
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/arm/
Dcpu-capacity.txt15 2 - CPU capacity definition
38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
69 #address-cells = <2>;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/mfd/
Domap-usb-host.txt29 "ohci-tll-2pin-datse0",
30 "ohci-tll-2pin-dpdm",
40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
47 * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
49 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
[all …]
/Linux-v6.1/drivers/net/wireless/intel/iwlwifi/fw/api/
Drs.h14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
22 * for BPSK (MCS 0) with 2 spatial
28 IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK = BIT(2),
35 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
36 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
37 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
[all …]
/Linux-v6.1/tools/testing/selftests/intel_pstate/
Drun.sh6 # state to the minimum supported frequency, in decrements of 100MHz. The
10 # or the requested frequency in MHz, the Actual frequency, as read from
22 #/tmp/result.3100:1:cpu MHz : 2899.980
23 #/tmp/result.3100:2:cpu MHz : 2900.000
28 # for consistency and modified to remove the extra MHz values. The result.X
43 echo $msg please run this as root >&2
60 grep MHz /proc/cpuinfo | sort -u > /tmp/result.freqs
62 if [ $num_freqs -ge 2 ]; then
80 # MAIN (ALL UNITS IN MHZ)
91 _max_freq=$(cpupower frequency-info -l | tail -1 | awk ' { print $2 } ')
[all …]

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