Lines Matching +full:2 +full:mhz
99 #define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
228 FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
229 FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
344 DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
455 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
497 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
508 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
536 GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
547 GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
564 GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
595 GATE_IP_CAM, 2, 0, 0),
609 GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
624 GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
632 GATE_IP_ISP, 2, 0, 0),
663 GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
670 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
671 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
672 PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
673 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
674 PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1),
675 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
676 PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1),
677 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
678 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
679 PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
680 PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2),
681 PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2),
682 PLL_35XX_RATE(24 * MHZ, 520000000, 260, 3, 2),
683 PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
684 PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
685 PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
686 PLL_35XX_RATE(24 * MHZ, 100000000, 200, 3, 4),
692 PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0),
693 PLL_36XX_RATE(24 * MHZ, 288000000, 96, 2, 2, 0),
694 PLL_36XX_RATE(24 * MHZ, 192000000, 128, 2, 3, 0),
695 PLL_36XX_RATE(24 * MHZ, 144000000, 96, 2, 3, 0),
696 PLL_36XX_RATE(24 * MHZ, 96000000, 128, 2, 4, 0),
697 PLL_36XX_RATE(24 * MHZ, 84000000, 112, 2, 4, 0),
698 PLL_36XX_RATE(24 * MHZ, 80000003, 106, 2, 4, 43691),
699 PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
700 PLL_36XX_RATE(24 * MHZ, 67737598, 270, 3, 5, 62285),
701 PLL_36XX_RATE(24 * MHZ, 65535999, 174, 2, 5, 49982),
702 PLL_36XX_RATE(24 * MHZ, 50000000, 200, 3, 5, 0),
703 PLL_36XX_RATE(24 * MHZ, 49152002, 131, 2, 5, 4719),
704 PLL_36XX_RATE(24 * MHZ, 48000000, 128, 2, 5, 0),
705 PLL_36XX_RATE(24 * MHZ, 45158401, 180, 3, 5, 41524),
711 PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0),
712 PLL_36XX_RATE(24 * MHZ, 533000000, 266, 3, 2, 32768),
713 PLL_36XX_RATE(24 * MHZ, 519230987, 173, 2, 2, 5046),
714 PLL_36XX_RATE(24 * MHZ, 500000000, 250, 3, 2, 0),
715 PLL_36XX_RATE(24 * MHZ, 445500000, 148, 2, 2, 32768),
716 PLL_36XX_RATE(24 * MHZ, 445055007, 148, 2, 2, 23047),
717 PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0),
718 PLL_36XX_RATE(24 * MHZ, 371250000, 123, 2, 2, 49152),
719 PLL_36XX_RATE(24 * MHZ, 370878997, 185, 3, 2, 28803),
720 PLL_36XX_RATE(24 * MHZ, 340000000, 170, 3, 2, 0),
721 PLL_36XX_RATE(24 * MHZ, 335000015, 111, 2, 2, 43691),
722 PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0),
723 PLL_36XX_RATE(24 * MHZ, 330000000, 110, 2, 2, 0),
724 PLL_36XX_RATE(24 * MHZ, 320000015, 106, 2, 2, 43691),
725 PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0),
726 PLL_36XX_RATE(24 * MHZ, 275000000, 275, 3, 3, 0),
727 PLL_36XX_RATE(24 * MHZ, 222750000, 148, 2, 3, 32768),
728 PLL_36XX_RATE(24 * MHZ, 222528007, 148, 2, 3, 23069),
729 PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0),
730 PLL_36XX_RATE(24 * MHZ, 148500000, 99, 2, 3, 0),
731 PLL_36XX_RATE(24 * MHZ, 148352005, 98, 2, 3, 59070),
732 PLL_36XX_RATE(24 * MHZ, 108000000, 144, 2, 4, 0),
733 PLL_36XX_RATE(24 * MHZ, 74250000, 99, 2, 4, 0),
734 PLL_36XX_RATE(24 * MHZ, 74176002, 98, 2, 4, 59070),
735 PLL_36XX_RATE(24 * MHZ, 54054000, 216, 3, 5, 14156),
736 PLL_36XX_RATE(24 * MHZ, 54000000, 144, 2, 5, 0),
907 DIV(CLK_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus", DIV_DMC1, 19, 2),
1030 GATE_IP_ISP0, 2, CLK_IGNORE_UNUSED, 0),