Home
last modified time | relevance | path

Searched +full:26 +full:mhz (Results 1 – 25 of 579) sorted by relevance

12345678910>>...24

/Linux-v6.6/Documentation/devicetree/bindings/clock/
Dsamsung,exynos850-clock.yaml20 two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
71 - description: External reference clock (26 MHz)
87 - description: External reference clock (26 MHz)
105 - description: External reference clock (26 MHz)
123 - description: External reference clock (26 MHz)
141 - description: External reference clock (26 MHz)
165 - description: External reference clock (26 MHz)
183 - description: External reference clock (26 MHz)
201 - description: External reference clock (26 MHz)
225 - description: External reference clock (26 MHz)
[all …]
Dsamsung,exynosautov9-clock.yaml20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
70 - description: External reference clock (26 MHz)
86 - description: External reference clock (26 MHz)
104 - description: External reference clock (26 MHz)
122 - description: External reference clock (26 MHz)
142 - description: External reference clock (26 MHz)
164 - description: External reference clock (26 MHz)
186 - description: External reference clock (26 MHz)
206 - description: External reference clock (26 MHz)
226 - description: External reference clock (26 MHz)
Dsamsung,exynos7885-clock.yaml20 is an external clock: OSCCLK (26 MHz). This external clock must be defined
64 - description: External reference clock (26 MHz)
80 - description: External reference clock (26 MHz)
102 - description: External reference clock (26 MHz)
128 - description: External reference clock (26 MHz)
Dnvidia,tegra20-car.yaml21 (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
/Linux-v6.6/drivers/net/wireless/ti/wl12xx/
Dwl12xx.h73 WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */
74 WL12XX_REFCLOCK_26 = 1, /* 26 MHz */
75 WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */
76 WL12XX_REFCLOCK_52 = 3, /* 52 MHz */
77 WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
78 WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
83 WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */
84 WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */
85 WL12XX_TCXOCLOCK_38_4 = 2, /* 38.4MHz */
86 WL12XX_TCXOCLOCK_52 = 3, /* 52 MHz */
[all …]
/Linux-v6.6/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
91 # 26 chars 29 lines
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
[all …]
/Linux-v6.6/drivers/net/wireless/intel/iwlwifi/fw/api/
Drs.h14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
146 * <nss, channel-width> pair (0 - 80mhz width and below, 1 - 160mhz).
[all …]
Dsta.h37 * will send all the frames in 20MHz even when FAT channel is requested.
38 * @STA_FLG_FAT_EN_20MHZ: no wide channels are supported, only 20 MHz
39 * @STA_FLG_FAT_EN_40MHZ: wide channels up to 40 MHz supported
40 * @STA_FLG_FAT_EN_80MHZ: wide channels up to 80 MHz supported
41 * @STA_FLG_FAT_EN_160MHZ: wide channels up to 160 MHz supported
87 STA_FLG_FAT_EN_20MHZ = (0 << 26),
88 STA_FLG_FAT_EN_40MHZ = (1 << 26),
89 STA_FLG_FAT_EN_80MHZ = (2 << 26),
90 STA_FLG_FAT_EN_160MHZ = (3 << 26),
91 STA_FLG_FAT_EN_MSK = (3 << 26),
/Linux-v6.6/drivers/media/tuners/
Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
45 1e 00 ? looks like operation register; write cmd here, read result from 1f-26
53 26 08 ?
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/Linux-v6.6/Documentation/devicetree/bindings/regulator/
Dmaxim,max8952.yaml62 - 0: 26 MHz
63 - 1: 13 MHz
64 - 2: 19.2 MHz
65 Defaults to 26 MHz if not specified.
/Linux-v6.6/arch/arm/boot/dts/arm/
Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
133 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
149 /* TIMER0 runs directly on the 25MHz chrystal */
155 /* TIMER1 runs @ 1MHz */
161 /* TIMER2 runs @ 1MHz */
179 /* The SIC is cascaded off IRQ 26 on the PIC */
[all …]
/Linux-v6.6/drivers/phy/ti/
Dphy-ti-pipe3.c84 #define MEM_OVRD_HS_RATE BIT(26)
85 #define MEM_OVRD_HS_RATE_SHIFT 26
186 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
187 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
188 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
189 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
190 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
191 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
196 {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
197 {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/phy/
Dmediatek,xsphy.yaml68 mediatek,src-ref-clk-mhz:
71 default: 26
94 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
176 mediatek,src-ref-clk-mhz = <26>;
/Linux-v6.6/drivers/clk/tegra/
Dclk-tegra30.c34 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
35 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
36 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
37 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
189 { 16800000, 1040000000, 495, 8, 1, 8 }, /* actual: 1039.5 MHz */
194 { 16800000, 832000000, 396, 8, 1, 8 }, /* actual: 831.6 MHz */
201 { 26000000, 624000000, 624, 26, 1, 8 },
206 { 26000000, 600000000, 600, 26, 1, 8 },
209 { 16800000, 520000000, 495, 16, 1, 8 }, /* actual: 519.75 MHz */
211 { 26000000, 520000000, 520, 26, 1, 8 },
[all …]
Dclk-tegra114.c84 #define PLLC_IDDQ_BIT 26
91 #define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
99 #define OSC_CTRL_PLL_REF_DIV_SHIFT 26
170 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
171 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
172 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
173 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
181 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
221 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
222 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
[all …]
Dclk-tegra124.c70 #define PLLC_IDDQ_BIT 26
173 { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
174 { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
175 { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
176 { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
177 { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
185 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
208 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
209 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
210 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
[all …]
Dclk-tegra20.c163 { 26000000, 600000000, 600, 26, 1, 8 },
171 { 26000000, 666000000, 666, 26, 1, 8 },
175 { 26000000, 600000000, 600, 26, 1, 8 },
183 { 26000000, 216000000, 432, 26, 2, 8 },
187 { 26000000, 432000000, 432, 26, 1, 8 },
202 { 26000000, 216000000, 216, 26, 1, 4 },
206 { 26000000, 594000000, 594, 26, 1, 8 },
210 { 26000000, 1000000000, 1000, 26, 1, 12 },
218 { 26000000, 480000000, 960, 26, 1, 0 },
227 { 26000000, 1000000000, 1000, 26, 1, 12 },
[all …]
/Linux-v6.6/include/linux/mmc/
Dmmc.h65 #define MMC_PROGRAM_CID 26 /* adtc R1 */
111 * [31:26] Always 0
139 #define R1_WP_VIOLATION (1 << 26) /* erx, c */
221 /* (CMD16,24,25,26,27) */
353 #define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */
354 #define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */
357 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
359 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
363 #define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
364 #define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */
[all …]
/Linux-v6.6/include/media/i2c/
Dtc358743.h33 u32 refclk_hz; /* 26 MHz, 27 MHz or 42 MHz */
61 * bps pr lane is 823.5 MHz, and can serve as a starting point.
86 /* Reset PHY automatically when TMDS clock passes 21 MHz.
/Linux-v6.6/include/linux/mfd/
Dti_am335x_tscadc.h73 #define STEPCONFIG_FIFO1 BIT(26)
138 * clock frequency: 26MHz / 8 = 3.25MHz
139 * clock period: 1 / 3.25MHz = 308ns
/Linux-v6.6/drivers/clk/imx/
Dclk-imx6sl.c116 * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz),
117 * ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since
123 * 396MHz -> 132MHz;
124 * 792MHz -> 158.4MHz;
125 * 996MHz -> 142.3MHz;
326 …hws[IMX6SL_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, p… in imx6sl_clocks_init()
348 …2D_OVG_PODF] = imx_clk_hw_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3); in imx6sl_clocks_init()
379 …[IMX6SL_CLK_GPU2D_OVG] = imx_clk_hw_gate2("gpu2d_ovg", "gpu2d_ovg_podf", base + 0x6c, 26); in imx6sl_clocks_init()
391 …[IMX6SL_CLK_MMDC_P1_IPG] = imx_clk_hw_gate2("mmdc_p1_ipg", "ipg", base + 0x74, 26); in imx6sl_clocks_init()
408 …[IMX6SL_CLK_UART_SERIAL] = imx_clk_hw_gate2("uart_serial", "uart_root", base + 0x7c, 26); in imx6sl_clocks_init()
[all …]
/Linux-v6.6/drivers/net/dsa/sja1105/
Dsja1105_clocking.c130 idiv.clksrc = 0x0A; /* 25MHz */ in sja1105_cgu_idiv_config()
357 /* RGMII: 125MHz for 1000, 25MHz for 100, 2.5MHz for 10 */ in sja1105_cgu_rgmii_tx_clk_config()
377 sja1105_packing(buf, &cmd->d32_ih, 26, 26, size, op); in sja1105_cfg_pad_mii_packing()
480 * 0 = 2.5MHz in sja1110_cfg_pad_mii_id_packing()
481 * 1 = 25MHz in sja1110_cfg_pad_mii_id_packing()
482 * 2 = 50MHz in sja1110_cfg_pad_mii_id_packing()
483 * 3 = 125MHz in sja1110_cfg_pad_mii_id_packing()
489 sja1105_packing(buf, &cmd->rxc_stable_ovr, 26, 26, size, op); in sja1110_cfg_pad_mii_id_packing()
596 /* 1000Mbps, IDIV disabled (125 MHz) */ in sja1105_rgmii_clocking_setup()
599 /* 100Mbps, IDIV enabled, divide by 1 (25 MHz) */ in sja1105_rgmii_clocking_setup()
[all …]
/Linux-v6.6/drivers/clk/mediatek/
Dclk-mt2701.c29 108 * MHZ),
31 400 * MHZ),
35 340 * MHZ),
37 340 * MHZ),
39 340 * MHZ),
41 27 * MHZ),
43 416 * MHZ),
45 143 * MHZ),
47 27 * MHZ),
79 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/display/bridge/
Dtoshiba,tc358767.yaml40 clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
/Linux-v6.6/drivers/phy/intel/
Dphy-intel-keembay-emmc.c22 #define OTAP_DLY_SEL_MASK GENMASK(26, 23)
59 unsigned int mhz; in keembay_emmc_phy_power() local
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
85 if (mhz <= 200 && mhz >= 170) in keembay_emmc_phy_power()
87 else if (mhz <= 170 && mhz >= 140) in keembay_emmc_phy_power()
89 else if (mhz <= 140 && mhz >= 110) in keembay_emmc_phy_power()
91 else if (mhz <= 110 && mhz >= 80) in keembay_emmc_phy_power()
93 else if (mhz <= 80 && mhz >= 50) in keembay_emmc_phy_power()
99 if (mhz > 175) in keembay_emmc_phy_power()
100 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz); in keembay_emmc_phy_power()
[all …]

12345678910>>...24