Lines Matching +full:26 +full:mhz

29 		108 * MHZ),
31 		400 * MHZ),
35 		340 * MHZ),
37 		340 * MHZ),
39 		340 * MHZ),
41 		27 * MHZ),
43 		416 * MHZ),
45 		143 * MHZ),
47 		27 * MHZ),
79 	FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
82 	FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
603 		0x012c, 18, 1, 26),
652 		26),
823 	GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
910 #define MT8590_PLL_FMAX		(2000 * MHZ)