Lines Matching +full:26 +full:mhz
116 * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz),
117 * ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since
123 * 396MHz -> 132MHz;
124 * 792MHz -> 158.4MHz;
125 * 996MHz -> 142.3MHz;
326 …hws[IMX6SL_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, p… in imx6sl_clocks_init()
348 …2D_OVG_PODF] = imx_clk_hw_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3); in imx6sl_clocks_init()
379 …[IMX6SL_CLK_GPU2D_OVG] = imx_clk_hw_gate2("gpu2d_ovg", "gpu2d_ovg_podf", base + 0x6c, 26); in imx6sl_clocks_init()
391 …[IMX6SL_CLK_MMDC_P1_IPG] = imx_clk_hw_gate2("mmdc_p1_ipg", "ipg", base + 0x74, 26); in imx6sl_clocks_init()
408 …[IMX6SL_CLK_UART_SERIAL] = imx_clk_hw_gate2("uart_serial", "uart_root", base + 0x7c, 26); in imx6sl_clocks_init()
422 /* Ensure the AHB clk is at 132MHz. */ in imx6sl_clocks_init()