/Linux-v5.10/drivers/phy/marvell/ |
D | phy-mvebu-cp110-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Antoine Tenart <antoine.tenart@free-electrons.com> 8 #include <linux/arm-smccc.h> 19 /* Relative to priv->base */ 36 #define MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY BIT(2) 84 #define MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN BIT(2) 107 /* Relative to priv->regmap */ 110 #define MVEBU_COMPHY_CONF1_USB_PCIE BIT(2) /* 0: Ethernet/SATA */ 128 * A lane is described by the following bitfields: 129 * [ 1- 0]: COMPHY polarity invertion [all …]
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D | phy-mvebu-a3700-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0 9 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart. 13 #include <linux/arm-smccc.h> 23 #define MVEBU_A3700_COMPHY_PORTS 2 43 #define COMPHY_FW_SPEED_3_125G 2 /* SGMII 2.5G */ 53 ((speed) << 2)) 58 unsigned int lane; member 67 .lane = _lane, \ 81 /* lane 0 */ 88 /* lane 1 */ [all …]
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D | phy-armada38x-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0 28 #define COMPHY_STAT1_PLL_RDY_RX BIT(2) 46 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member 58 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument 60 struct a38x_comphy *priv = lane->priv; in a38x_set_conf() 63 if (priv->conf) { in a38x_set_conf() 64 conf = readl_relaxed(priv->conf); in a38x_set_conf() 66 conf |= BIT(lane->port); in a38x_set_conf() 68 conf &= ~BIT(lane->port); in a38x_set_conf() 69 writel(conf, priv->conf); in a38x_set_conf() [all …]
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/Linux-v5.10/Documentation/devicetree/bindings/media/i2c/ |
D | st,st-mipid02.txt | 1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge 3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a 4 time. Active port input stream will be de-serialized and its content outputted 6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second 7 input port is a single lane 800Mbps. Both ports support clock and data lane 8 polarity swap. First port also supports data lane swap. 11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit. 14 - compatible: shall be "st,st-mipid02" 15 - clocks: reference to the xclk input clock. 16 - clock-names: shall be "xclk". [all …]
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/Linux-v5.10/drivers/gpu/drm/bridge/analogix/ |
D | analogix_dp_core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 82 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd() 84 if (!dp->force_hpd) in analogix_dp_detect_hpd() 85 return -ETIMEDOUT; in analogix_dp_detect_hpd() 92 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd() 97 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd() 98 return -EINVAL; in analogix_dp_detect_hpd() 101 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd() 111 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr() 113 dev_err(dp->dev, "failed to get PSR version, disable it\n"); in analogix_dp_detect_sink_psr() [all …]
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/Linux-v5.10/drivers/phy/ |
D | phy-xgene.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * AppliedMicro X-Gene Multi-purpose PHY driver 10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes. 19 * ----------------- 20 * | Internal | |------| 21 * | Ref PLL CMU |----| | ------------- --------- 22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes| 23 * | | | | --------- 24 * External Clock ------| | ------------- 25 * |------| [all …]
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/Linux-v5.10/drivers/phy/tegra/ |
D | xusb-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only 86 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL2(x) ((x) < 2 ? 0x078 + (x) * 4 : \ 92 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL5(x) ((x) < 2 ? 0x090 + (x) * 4 : \ 96 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(x) ((x) < 2 ? 0x098 + (x) * 4 : \ 128 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2) 134 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT 2 158 #define XUSB_PADCTL_HSIC_PAD_CTL1_PD_TX (1 << 2) 229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable() 231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable() 251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable() [all …]
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D | xusb-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. 21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0) 33 #define USB2_PORT_SHIFT(x) ((x) * 2) 58 USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \ 59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \ 65 #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3) 80 #define USB2_OTG_PD_DR BIT(2) 159 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe() 161 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe() [all …]
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D | xusb-tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only 25 ((x) ? (11 + ((x) - 1) * 6) : 0) 59 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3)) 90 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2) 126 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 (1 << 2) 168 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD (1 << 2) 259 /* must be called under padctl->lock */ 262 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_enable() 267 if (pcie->enable > 0) { in tegra210_pex_uphy_enable() 268 pcie->enable++; in tegra210_pex_uphy_enable() [all …]
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/Linux-v5.10/drivers/phy/xilinx/ |
D | phy-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT. 5 * Copyright (C) 2018-2020 Xilinx Inc. 26 #include <dt-bindings/phy/phy.h> 29 * Lane Registers 32 /* TX De-emphasis parameters */ 46 #define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2) 137 #define PROT_BUS_WIDTH_SHIFT 2 151 #define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */ 152 #define XPSGTR_TYPE_SATA_1 3 /* SATA controller lane 1 */ [all …]
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/Linux-v5.10/drivers/phy/rockchip/ |
D | phy-rockchip-typec.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 * Author: Chris Zhong <zyw@rock-chips.com> 5 * Kever Yang <kever.yang@rock-chips.com> 7 * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock 8 * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has 24 * 2. DP only mode: 34 * This Type-C PHY driver supports normal and flip orientation. The orientation 40 #include <linux/clk-provider.h> 58 #define CMN_SSM_BANDGAP (0x21 << 2) 59 #define CMN_SSM_BIAS (0x22 << 2) [all …]
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/Linux-v5.10/drivers/gpu/drm/amd/display/dc/core/ |
D | dc_link_dp.c | 19 link->ctx->logger 38 /* to avoid infinite loop where-in the receiver 78 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_eq_training_aux_rd_interval() 79 /* DP 1.2 or later - retrieve delay through in get_eq_training_aux_rd_interval() 133 struct encoder_feature_support *features = &link->link_enc->features; in decide_eq_training_pattern() 134 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; in decide_eq_training_pattern() 136 if (features->flags.bits.IS_TPS3_CAPABLE) in decide_eq_training_pattern() 139 if (features->flags.bits.IS_TPS4_CAPABLE) in decide_eq_training_pattern() 142 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED && in decide_eq_training_pattern() 146 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED && in decide_eq_training_pattern() [all …]
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/Linux-v5.10/drivers/net/ethernet/ti/ |
D | netcp_xgbepcsr.c | 1 // SPDX-License-Identifier: GPL-2.0 7 * WingMan Kwok <w-kwok2@ti.com> 17 /* PCS-R registers */ 26 #define MASK_WID_SH(w, s) (((1 << w) - 1) << s) 146 /* lane is 0 based */ 148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument 152 /* lane setup */ in netcp_xgbe_serdes_lane_config() 156 (0x200 * lane), in netcp_xgbe_serdes_lane_config() 162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config() 166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config() [all …]
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/Linux-v5.10/drivers/thunderbolt/ |
D | lc.c | 1 // SPDX-License-Identifier: GPL-2.0 12 * tb_lc_read_uuid() - Read switch UUID from link controller common register 18 if (!sw->cap_lc) in tb_lc_read_uuid() 19 return -EINVAL; in tb_lc_read_uuid() 20 return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4); in tb_lc_read_uuid() 25 if (!sw->cap_lc) in read_lc_desc() 26 return -EINVAL; in read_lc_desc() 27 return tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1); in read_lc_desc() 32 struct tb_switch *sw = port->sw; in find_port_lc_cap() 43 phys = tb_phy_port_from_link(port->port); in find_port_lc_cap() [all …]
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/Linux-v5.10/drivers/media/platform/omap3isp/ |
D | omap3isp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 5 * TI OMAP3 ISP - Bus Configuration 25 * struct isp_parallel_cfg - Parallel interface configuration 26 * @data_lane_shift: Data lane shifter 27 * 0 - CAMEXT[13:0] -> CAM[13:0] 28 * 2 - CAMEXT[13:2] -> CAM[11:0] 29 * 4 - CAMEXT[13:4] -> CAM[9:0] 30 * 6 - CAMEXT[13:6] -> CAM[7:0] 32 * 0 - Sample on rising edge, 1 - Sample on falling edge 34 * 0 - Active high, 1 - Active low [all …]
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/Linux-v5.10/drivers/net/dsa/mv88e6xxx/ |
D | serdes.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 42 /* 10GBASE-R and 10GBASE-X4/X2 */ 46 /* 1000BASE-X and SGMII */ 70 #define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE BIT(2) 81 u8 lane, unsigned int mode, 85 u8 lane, unsigned int mode, 89 u8 lane, struct phylink_link_state *state); 91 u8 lane, struct phylink_link_state *state); 93 u8 lane); 95 u8 lane); [all …]
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D | serdes.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 37 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument 41 return mv88e6xxx_phy_read(chip, lane, reg_c45, val); in mv88e6390_serdes_read() 45 int lane, int device, int reg, u16 val) in mv88e6390_serdes_write() argument 49 return mv88e6xxx_phy_write(chip, lane, reg_c45, val); in mv88e6390_serdes_write() 57 state->link = !!(status & MV88E6390_SGMII_PHY_STATUS_LINK); in mv88e6xxx_serdes_pcs_get_state() 58 state->duplex = status & in mv88e6xxx_serdes_pcs_get_state() 63 state->pause |= MLO_PAUSE_TX; in mv88e6xxx_serdes_pcs_get_state() 65 state->pause |= MLO_PAUSE_RX; in mv88e6xxx_serdes_pcs_get_state() 69 if (state->interface == PHY_INTERFACE_MODE_2500BASEX) in mv88e6xxx_serdes_pcs_get_state() [all …]
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/Linux-v5.10/drivers/gpu/drm/i915/display/ |
D | intel_dp_link_training.c | 2 * Copyright © 2008-2015 Intel Corporation 33 link_status[0], link_status[1], link_status[2], in intel_dp_dump_link_status() 58 int lane; in intel_dp_get_adjust_train() local 62 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_dp_get_adjust_train() 63 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); in intel_dp_get_adjust_train() 64 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); in intel_dp_get_adjust_train() 67 preemph_max = intel_dp->preemph_max(intel_dp); in intel_dp_get_adjust_train() 68 drm_WARN_ON_ONCE(&i915->drm, in intel_dp_get_adjust_train() 77 voltage_max = intel_dp->voltage_max(intel_dp); in intel_dp_get_adjust_train() 78 drm_WARN_ON_ONCE(&i915->drm, in intel_dp_get_adjust_train() [all …]
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/Linux-v5.10/drivers/pinctrl/tegra/ |
D | pinctrl-tegra-xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only 17 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 20 #include "../pinctrl-utils.h" 88 struct phy *phys[2]; 96 writel(value, padctl->regs + offset); in padctl_writel() 102 return readl(padctl->regs + offset); in padctl_readl() 109 return padctl->soc->num_pins; in tegra_xusb_padctl_get_groups_count() 117 return padctl->soc->pins[group].name; in tegra_xusb_padctl_get_group_name() 126 * For the tegra-xusb pad controller groups are synonymous in tegra_xusb_padctl_get_group_pins() 127 * with lanes/pins and there is always one lane/pin per group. in tegra_xusb_padctl_get_group_pins() [all …]
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/Linux-v5.10/Documentation/devicetree/bindings/phy/ |
D | phy-cadence-sierra.txt | 2 ----------------------- 5 - compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform 6 Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC. 7 - resets: Must contain an entry for each in reset-names. 9 - reset-names: Must include "sierra_reset" and "sierra_apb". 13 - reg: register range for the PHY. 14 - #address-cells: Must be 1 15 - #size-cells: Must be 0 18 - clocks: Must contain an entry in clock-names. 19 See ../clocks/clock-bindings.txt for details. [all …]
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D | phy-mvebu-comphy.txt | 2 -------------------- 12 - compatible: should be one of: 13 * "marvell,comphy-cp110" for Armada 7k/8k 14 * "marvell,comphy-a3700" for Armada 3700 15 - reg: should contain the COMPHY register(s) location(s) and length(s). 17 * 4 entries for Armada 3700 along with the corresponding reg-names 20 * Lane 1 (PCIe/GbE) 21 * Lane 0 (USB3/GbE) 22 * Lane 2 (SATA/USB3) 23 - marvell,system-controller: should contain a phandle to the system [all …]
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/Linux-v5.10/drivers/gpu/drm/bridge/ |
D | tc358775.c | 1 // SPDX-License-Identifier: GPL-2.0 35 /* DSI D-PHY Layer Registers */ 36 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */ 37 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */ 38 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */ 39 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */ 40 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */ 41 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */ 43 #define CLW_CNTRL 0x0040 /* Clock Lane Control */ 44 #define D0W_CNTRL 0x0044 /* Data Lane 0 Control */ [all …]
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/Linux-v5.10/Documentation/devicetree/bindings/media/ |
D | qcom,camss.txt | 5 - compatible: 9 - "qcom,msm8916-camss" 10 - "qcom,msm8996-camss" 11 - reg: 13 Value type: <prop-encoded-array> 14 Definition: Register ranges as listed in the reg-names property. 15 - reg-names: 19 - "csiphy0" 20 - "csiphy0_clk_mux" 21 - "csiphy1" [all …]
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/Linux-v5.10/tools/perf/pmu-events/arch/x86/cascadelakex/ |
D | uncore-other.json | 4 "Counter": "0,1,2,3", 10 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.… 11 "Counter": "0,1,2,3", 21 "Counter": "0,1,2,3", 31 "Counter": "0,1,2,3", 41 "Counter": "0,1,2,3", 52 "Counter": "0,1,2,3", 63 "Counter": "0,1,2,3", 72 "Counter": "0,1,2,3", 81 "Counter": "0,1,2,3", [all …]
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/Linux-v5.10/tools/perf/pmu-events/arch/x86/skylakex/ |
D | uncore-other.json | 4 "Counter": "0,1,2,3", 10 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.… 11 "Counter": "0,1,2,3", 21 "Counter": "0,1,2,3", 31 "Counter": "0,1,2,3", 41 "Counter": "0,1,2,3", 52 "Counter": "0,1,2,3", 63 "Counter": "0,1,2,3", 72 "Counter": "0,1,2,3", 81 "Counter": "0,1,2,3", [all …]
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