Lines Matching +full:2 +full:- +full:lane
1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
19 /* Relative to priv->base */
36 #define MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY BIT(2)
84 #define MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN BIT(2)
107 /* Relative to priv->regmap */
110 #define MVEBU_COMPHY_CONF1_USB_PCIE BIT(2) /* 0: Ethernet/SATA */
128 * A lane is described by the following bitfields:
129 * [ 1- 0]: COMPHY polarity invertion
130 * [ 2- 7]: COMPHY speed
131 * [ 5-11]: COMPHY port index
132 * [12-16]: COMPHY mode
134 * [18-20]: PCIe width (x1, x2, x4)
138 #define COMPHY_FW_SPEED_OFFSET 2
139 #define COMPHY_FW_SPEED_MASK GENMASK(7, 2)
142 #define COMPHY_FW_SPEED_3125 2
180 unsigned lane; member
188 .lane = _lane, \
198 .lane = _lane, \
202 .mux = -1, \
207 /* lane 0 */
212 /* lane 1 */
217 ETH_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
218 ETH_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
219 /* lane 2 */
220 ETH_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
221 ETH_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
222 ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, 0x1, COMPHY_FW_MODE_RXAUI),
223 ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GBASER, 0x1, COMPHY_FW_MODE_XFI),
224 GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
225 GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
226 GEN_CONF(2, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
227 /* lane 3 */
234 /* lane 4 */
243 ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
244 ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GBASER, -1, COMPHY_FW_MODE_XFI),
245 /* lane 5 */
248 ETH_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
249 ETH_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
250 GEN_CONF(5, 2, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
272 unsigned long lane, unsigned long mode) in mvebu_comphy_smc() argument
277 arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res); in mvebu_comphy_smc()
284 return -EOPNOTSUPP; in mvebu_comphy_smc()
286 return -EINVAL; in mvebu_comphy_smc()
290 static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port, in mvebu_comphy_get_mode() argument
304 if (conf->lane == lane && in mvebu_comphy_get_mode()
305 conf->port == port && in mvebu_comphy_get_mode()
306 conf->mode == mode && in mvebu_comphy_get_mode()
307 (conf->submode == submode || ignore_submode)) in mvebu_comphy_get_mode()
312 return -EINVAL; in mvebu_comphy_get_mode()
315 return conf->fw_mode; in mvebu_comphy_get_mode()
317 return conf->mux; in mvebu_comphy_get_mode()
320 static inline int mvebu_comphy_get_mux(int lane, int port, in mvebu_comphy_get_mux() argument
323 return mvebu_comphy_get_mode(false, lane, port, mode, submode); in mvebu_comphy_get_mux()
326 static inline int mvebu_comphy_get_fw_mode(int lane, int port, in mvebu_comphy_get_fw_mode() argument
329 return mvebu_comphy_get_mode(true, lane, port, mode, submode); in mvebu_comphy_get_fw_mode()
332 static int mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane) in mvebu_comphy_ethernet_init_reset() argument
334 struct mvebu_comphy_priv *priv = lane->priv; in mvebu_comphy_ethernet_init_reset()
337 regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); in mvebu_comphy_ethernet_init_reset()
340 regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); in mvebu_comphy_ethernet_init_reset()
343 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); in mvebu_comphy_ethernet_init_reset()
352 switch (lane->submode) { in mvebu_comphy_ethernet_init_reset()
373 dev_err(priv->dev, in mvebu_comphy_ethernet_init_reset()
374 "unsupported comphy submode (%d) on lane %d\n", in mvebu_comphy_ethernet_init_reset()
375 lane->submode, in mvebu_comphy_ethernet_init_reset()
376 lane->id); in mvebu_comphy_ethernet_init_reset()
377 return -ENOTSUPP; in mvebu_comphy_ethernet_init_reset()
380 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); in mvebu_comphy_ethernet_init_reset()
382 if (lane->submode == PHY_INTERFACE_MODE_RXAUI) { in mvebu_comphy_ethernet_init_reset()
383 regmap_read(priv->regmap, MVEBU_COMPHY_SD1_CTRL1, &val); in mvebu_comphy_ethernet_init_reset()
385 switch (lane->id) { in mvebu_comphy_ethernet_init_reset()
386 case 2: in mvebu_comphy_ethernet_init_reset()
395 dev_err(priv->dev, in mvebu_comphy_ethernet_init_reset()
396 "RXAUI is not supported on comphy lane %d\n", in mvebu_comphy_ethernet_init_reset()
397 lane->id); in mvebu_comphy_ethernet_init_reset()
398 return -EINVAL; in mvebu_comphy_ethernet_init_reset()
401 regmap_write(priv->regmap, MVEBU_COMPHY_SD1_CTRL1, val); in mvebu_comphy_ethernet_init_reset()
405 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_ethernet_init_reset()
409 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_ethernet_init_reset()
411 /* de-assert reset */ in mvebu_comphy_ethernet_init_reset()
412 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_ethernet_init_reset()
415 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_ethernet_init_reset()
421 regmap_read(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), &val); in mvebu_comphy_ethernet_init_reset()
423 regmap_write(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), val); in mvebu_comphy_ethernet_init_reset()
426 val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); in mvebu_comphy_ethernet_init_reset()
428 if (lane->submode == PHY_INTERFACE_MODE_10GBASER) in mvebu_comphy_ethernet_init_reset()
430 writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); in mvebu_comphy_ethernet_init_reset()
433 val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); in mvebu_comphy_ethernet_init_reset()
438 writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); in mvebu_comphy_ethernet_init_reset()
440 val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); in mvebu_comphy_ethernet_init_reset()
443 writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); in mvebu_comphy_ethernet_init_reset()
448 static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane) in mvebu_comphy_init_plls() argument
450 struct mvebu_comphy_priv *priv = lane->priv; in mvebu_comphy_init_plls()
454 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); in mvebu_comphy_init_plls()
458 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); in mvebu_comphy_init_plls()
461 readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id), in mvebu_comphy_init_plls()
468 return -ETIMEDOUT; in mvebu_comphy_init_plls()
471 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_init_plls()
473 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_init_plls()
476 readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id), in mvebu_comphy_init_plls()
480 return -ETIMEDOUT; in mvebu_comphy_init_plls()
482 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_init_plls()
484 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_init_plls()
491 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_comphy_set_mode_sgmii() local
492 struct mvebu_comphy_priv *priv = lane->priv; in mvebu_comphy_set_mode_sgmii()
496 err = mvebu_comphy_ethernet_init_reset(lane); in mvebu_comphy_set_mode_sgmii()
500 val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); in mvebu_comphy_set_mode_sgmii()
503 writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); in mvebu_comphy_set_mode_sgmii()
505 val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); in mvebu_comphy_set_mode_sgmii()
507 writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); in mvebu_comphy_set_mode_sgmii()
509 regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); in mvebu_comphy_set_mode_sgmii()
512 regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); in mvebu_comphy_set_mode_sgmii()
514 val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); in mvebu_comphy_set_mode_sgmii()
517 writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); in mvebu_comphy_set_mode_sgmii()
519 return mvebu_comphy_init_plls(lane); in mvebu_comphy_set_mode_sgmii()
524 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_comphy_set_mode_rxaui() local
525 struct mvebu_comphy_priv *priv = lane->priv; in mvebu_comphy_set_mode_rxaui()
529 err = mvebu_comphy_ethernet_init_reset(lane); in mvebu_comphy_set_mode_rxaui()
533 val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); in mvebu_comphy_set_mode_rxaui()
536 writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); in mvebu_comphy_set_mode_rxaui()
538 val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); in mvebu_comphy_set_mode_rxaui()
540 writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); in mvebu_comphy_set_mode_rxaui()
542 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); in mvebu_comphy_set_mode_rxaui()
544 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); in mvebu_comphy_set_mode_rxaui()
546 val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); in mvebu_comphy_set_mode_rxaui()
548 writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); in mvebu_comphy_set_mode_rxaui()
550 val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); in mvebu_comphy_set_mode_rxaui()
553 writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); in mvebu_comphy_set_mode_rxaui()
555 val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); in mvebu_comphy_set_mode_rxaui()
561 writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); in mvebu_comphy_set_mode_rxaui()
563 val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id)); in mvebu_comphy_set_mode_rxaui()
565 writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id)); in mvebu_comphy_set_mode_rxaui()
567 val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); in mvebu_comphy_set_mode_rxaui()
570 writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); in mvebu_comphy_set_mode_rxaui()
572 return mvebu_comphy_init_plls(lane); in mvebu_comphy_set_mode_rxaui()
577 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_comphy_set_mode_10gbaser() local
578 struct mvebu_comphy_priv *priv = lane->priv; in mvebu_comphy_set_mode_10gbaser()
582 err = mvebu_comphy_ethernet_init_reset(lane); in mvebu_comphy_set_mode_10gbaser()
586 val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); in mvebu_comphy_set_mode_10gbaser()
589 writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); in mvebu_comphy_set_mode_10gbaser()
591 val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); in mvebu_comphy_set_mode_10gbaser()
593 writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); in mvebu_comphy_set_mode_10gbaser()
596 val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id)); in mvebu_comphy_set_mode_10gbaser()
598 writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id)); in mvebu_comphy_set_mode_10gbaser()
600 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); in mvebu_comphy_set_mode_10gbaser()
602 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); in mvebu_comphy_set_mode_10gbaser()
605 val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); in mvebu_comphy_set_mode_10gbaser()
607 writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); in mvebu_comphy_set_mode_10gbaser()
609 val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); in mvebu_comphy_set_mode_10gbaser()
614 writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); in mvebu_comphy_set_mode_10gbaser()
616 val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id)); in mvebu_comphy_set_mode_10gbaser()
619 writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id)); in mvebu_comphy_set_mode_10gbaser()
621 val = readl(priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id)); in mvebu_comphy_set_mode_10gbaser()
624 writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id)); in mvebu_comphy_set_mode_10gbaser()
627 val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id)); in mvebu_comphy_set_mode_10gbaser()
631 writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id)); in mvebu_comphy_set_mode_10gbaser()
633 val = readl(priv->base + MVEBU_COMPHY_GEN1_S5(lane->id)); in mvebu_comphy_set_mode_10gbaser()
635 writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id)); in mvebu_comphy_set_mode_10gbaser()
637 val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); in mvebu_comphy_set_mode_10gbaser()
647 writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); in mvebu_comphy_set_mode_10gbaser()
649 val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id)); in mvebu_comphy_set_mode_10gbaser()
651 writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id)); in mvebu_comphy_set_mode_10gbaser()
653 val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); in mvebu_comphy_set_mode_10gbaser()
656 writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); in mvebu_comphy_set_mode_10gbaser()
658 val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); in mvebu_comphy_set_mode_10gbaser()
660 writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); in mvebu_comphy_set_mode_10gbaser()
663 val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id)); in mvebu_comphy_set_mode_10gbaser()
666 writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id)); in mvebu_comphy_set_mode_10gbaser()
669 val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id)); in mvebu_comphy_set_mode_10gbaser()
671 writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id)); in mvebu_comphy_set_mode_10gbaser()
673 val = readl(priv->base + MVEBU_COMPHY_TX_PRESET(lane->id)); in mvebu_comphy_set_mode_10gbaser()
676 writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id)); in mvebu_comphy_set_mode_10gbaser()
678 val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id)); in mvebu_comphy_set_mode_10gbaser()
680 writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id)); in mvebu_comphy_set_mode_10gbaser()
682 val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id)); in mvebu_comphy_set_mode_10gbaser()
685 writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id)); in mvebu_comphy_set_mode_10gbaser()
687 val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id)); in mvebu_comphy_set_mode_10gbaser()
690 writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id)); in mvebu_comphy_set_mode_10gbaser()
692 val = readl(priv->base + MVEBU_COMPHY_DME(lane->id)); in mvebu_comphy_set_mode_10gbaser()
694 writel(val, priv->base + MVEBU_COMPHY_DME(lane->id)); in mvebu_comphy_set_mode_10gbaser()
696 val = readl(priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id)); in mvebu_comphy_set_mode_10gbaser()
698 writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id)); in mvebu_comphy_set_mode_10gbaser()
700 val = readl(priv->base + MVEBU_SP_CALIB(lane->id)); in mvebu_comphy_set_mode_10gbaser()
704 writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); in mvebu_comphy_set_mode_10gbaser()
706 writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); in mvebu_comphy_set_mode_10gbaser()
709 val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); in mvebu_comphy_set_mode_10gbaser()
712 writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); in mvebu_comphy_set_mode_10gbaser()
714 return mvebu_comphy_init_plls(lane); in mvebu_comphy_set_mode_10gbaser()
719 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_comphy_power_on_legacy() local
720 struct mvebu_comphy_priv *priv = lane->priv; in mvebu_comphy_power_on_legacy()
724 mux = mvebu_comphy_get_mux(lane->id, lane->port, in mvebu_comphy_power_on_legacy()
725 lane->mode, lane->submode); in mvebu_comphy_power_on_legacy()
727 return -ENOTSUPP; in mvebu_comphy_power_on_legacy()
729 regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val); in mvebu_comphy_power_on_legacy()
730 val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id)); in mvebu_comphy_power_on_legacy()
731 regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val); in mvebu_comphy_power_on_legacy()
733 regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val); in mvebu_comphy_power_on_legacy()
734 val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id)); in mvebu_comphy_power_on_legacy()
735 val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id); in mvebu_comphy_power_on_legacy()
736 regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val); in mvebu_comphy_power_on_legacy()
738 switch (lane->submode) { in mvebu_comphy_power_on_legacy()
750 return -ENOTSUPP; in mvebu_comphy_power_on_legacy()
754 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_power_on_legacy()
756 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_power_on_legacy()
763 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_comphy_power_on() local
764 struct mvebu_comphy_priv *priv = lane->priv; in mvebu_comphy_power_on()
769 fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port, in mvebu_comphy_power_on()
770 lane->mode, lane->submode); in mvebu_comphy_power_on()
775 switch (lane->mode) { in mvebu_comphy_power_on()
777 switch (lane->submode) { in mvebu_comphy_power_on()
779 dev_dbg(priv->dev, "set lane %d to RXAUI mode\n", in mvebu_comphy_power_on()
780 lane->id); in mvebu_comphy_power_on()
784 dev_dbg(priv->dev, "set lane %d to 1000BASE-X mode\n", in mvebu_comphy_power_on()
785 lane->id); in mvebu_comphy_power_on()
789 dev_dbg(priv->dev, "set lane %d to 2500BASE-X mode\n", in mvebu_comphy_power_on()
790 lane->id); in mvebu_comphy_power_on()
794 dev_dbg(priv->dev, "set lane %d to 10GBASE-R mode\n", in mvebu_comphy_power_on()
795 lane->id); in mvebu_comphy_power_on()
799 dev_err(priv->dev, "unsupported Ethernet mode (%d)\n", in mvebu_comphy_power_on()
800 lane->submode); in mvebu_comphy_power_on()
801 return -ENOTSUPP; in mvebu_comphy_power_on()
803 fw_param = COMPHY_FW_PARAM_ETH(fw_mode, lane->port, fw_speed); in mvebu_comphy_power_on()
807 dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id); in mvebu_comphy_power_on()
808 fw_param = COMPHY_FW_PARAM(fw_mode, lane->port); in mvebu_comphy_power_on()
811 dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id); in mvebu_comphy_power_on()
812 fw_param = COMPHY_FW_PARAM(fw_mode, lane->port); in mvebu_comphy_power_on()
815 dev_dbg(priv->dev, "set lane %d to PCIe mode (x%d)\n", lane->id, in mvebu_comphy_power_on()
816 lane->submode); in mvebu_comphy_power_on()
817 fw_param = COMPHY_FW_PARAM_PCIE(fw_mode, lane->port, in mvebu_comphy_power_on()
818 lane->submode); in mvebu_comphy_power_on()
821 dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode); in mvebu_comphy_power_on()
822 return -ENOTSUPP; in mvebu_comphy_power_on()
825 ret = mvebu_comphy_smc(COMPHY_SIP_POWER_ON, priv->cp_phys, lane->id, in mvebu_comphy_power_on()
830 if (ret == -EOPNOTSUPP) in mvebu_comphy_power_on()
831 dev_err(priv->dev, in mvebu_comphy_power_on()
834 dev_warn(priv->dev, in mvebu_comphy_power_on()
836 lane->id, lane->mode, ret); in mvebu_comphy_power_on()
846 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_comphy_set_mode() local
851 if (mvebu_comphy_get_fw_mode(lane->id, lane->port, mode, submode) < 0) in mvebu_comphy_set_mode()
852 return -EINVAL; in mvebu_comphy_set_mode()
854 lane->mode = mode; in mvebu_comphy_set_mode()
855 lane->submode = submode; in mvebu_comphy_set_mode()
858 if (mode == PHY_MODE_PCIE && !lane->submode) in mvebu_comphy_set_mode()
859 lane->submode = 1; in mvebu_comphy_set_mode()
866 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_comphy_power_off_legacy() local
867 struct mvebu_comphy_priv *priv = lane->priv; in mvebu_comphy_power_off_legacy()
870 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_power_off_legacy()
874 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_power_off_legacy()
876 regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val); in mvebu_comphy_power_off_legacy()
877 val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id)); in mvebu_comphy_power_off_legacy()
878 regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val); in mvebu_comphy_power_off_legacy()
880 regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val); in mvebu_comphy_power_off_legacy()
881 val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id)); in mvebu_comphy_power_off_legacy()
882 regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val); in mvebu_comphy_power_off_legacy()
889 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_comphy_power_off() local
890 struct mvebu_comphy_priv *priv = lane->priv; in mvebu_comphy_power_off()
893 ret = mvebu_comphy_smc(COMPHY_SIP_POWER_OFF, priv->cp_phys, in mvebu_comphy_power_off()
894 lane->id, 0); in mvebu_comphy_power_off()
912 struct mvebu_comphy_lane *lane; in mvebu_comphy_xlate() local
915 if (WARN_ON(args->args[0] >= MVEBU_COMPHY_PORTS)) in mvebu_comphy_xlate()
916 return ERR_PTR(-EINVAL); in mvebu_comphy_xlate()
922 lane = phy_get_drvdata(phy); in mvebu_comphy_xlate()
923 lane->port = args->args[0]; in mvebu_comphy_xlate()
932 priv->mg_domain_clk = devm_clk_get(priv->dev, "mg_clk"); in mvebu_comphy_init_clks()
933 if (IS_ERR(priv->mg_domain_clk)) in mvebu_comphy_init_clks()
934 return PTR_ERR(priv->mg_domain_clk); in mvebu_comphy_init_clks()
936 ret = clk_prepare_enable(priv->mg_domain_clk); in mvebu_comphy_init_clks()
940 priv->mg_core_clk = devm_clk_get(priv->dev, "mg_core_clk"); in mvebu_comphy_init_clks()
941 if (IS_ERR(priv->mg_core_clk)) { in mvebu_comphy_init_clks()
942 ret = PTR_ERR(priv->mg_core_clk); in mvebu_comphy_init_clks()
946 ret = clk_prepare_enable(priv->mg_core_clk); in mvebu_comphy_init_clks()
950 priv->axi_clk = devm_clk_get(priv->dev, "axi_clk"); in mvebu_comphy_init_clks()
951 if (IS_ERR(priv->axi_clk)) { in mvebu_comphy_init_clks()
952 ret = PTR_ERR(priv->axi_clk); in mvebu_comphy_init_clks()
956 ret = clk_prepare_enable(priv->axi_clk); in mvebu_comphy_init_clks()
963 clk_disable_unprepare(priv->mg_core_clk); in mvebu_comphy_init_clks()
966 clk_disable_unprepare(priv->mg_domain_clk); in mvebu_comphy_init_clks()
968 priv->mg_domain_clk = NULL; in mvebu_comphy_init_clks()
969 priv->mg_core_clk = NULL; in mvebu_comphy_init_clks()
970 priv->axi_clk = NULL; in mvebu_comphy_init_clks()
977 if (priv->axi_clk) in mvebu_comphy_disable_unprepare_clks()
978 clk_disable_unprepare(priv->axi_clk); in mvebu_comphy_disable_unprepare_clks()
980 if (priv->mg_core_clk) in mvebu_comphy_disable_unprepare_clks()
981 clk_disable_unprepare(priv->mg_core_clk); in mvebu_comphy_disable_unprepare_clks()
983 if (priv->mg_domain_clk) in mvebu_comphy_disable_unprepare_clks()
984 clk_disable_unprepare(priv->mg_domain_clk); in mvebu_comphy_disable_unprepare_clks()
995 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in mvebu_comphy_probe()
997 return -ENOMEM; in mvebu_comphy_probe()
999 priv->dev = &pdev->dev; in mvebu_comphy_probe()
1000 priv->regmap = in mvebu_comphy_probe()
1001 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in mvebu_comphy_probe()
1002 "marvell,system-controller"); in mvebu_comphy_probe()
1003 if (IS_ERR(priv->regmap)) in mvebu_comphy_probe()
1004 return PTR_ERR(priv->regmap); in mvebu_comphy_probe()
1006 priv->base = devm_ioremap_resource(&pdev->dev, res); in mvebu_comphy_probe()
1007 if (IS_ERR(priv->base)) in mvebu_comphy_probe()
1008 return PTR_ERR(priv->base); in mvebu_comphy_probe()
1016 if (ret == -EPROBE_DEFER) in mvebu_comphy_probe()
1018 dev_warn(&pdev->dev, "cannot initialize clocks\n"); in mvebu_comphy_probe()
1025 priv->cp_phys = res->start; in mvebu_comphy_probe()
1027 for_each_available_child_of_node(pdev->dev.of_node, child) { in mvebu_comphy_probe()
1028 struct mvebu_comphy_lane *lane; in mvebu_comphy_probe() local
1034 dev_err(&pdev->dev, "missing 'reg' property (%d)\n", in mvebu_comphy_probe()
1040 dev_err(&pdev->dev, "invalid 'reg' property\n"); in mvebu_comphy_probe()
1044 lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL); in mvebu_comphy_probe()
1045 if (!lane) { in mvebu_comphy_probe()
1047 ret = -ENOMEM; in mvebu_comphy_probe()
1051 phy = devm_phy_create(&pdev->dev, child, &mvebu_comphy_ops); in mvebu_comphy_probe()
1058 lane->priv = priv; in mvebu_comphy_probe()
1059 lane->mode = PHY_MODE_INVALID; in mvebu_comphy_probe()
1060 lane->submode = PHY_INTERFACE_MODE_NA; in mvebu_comphy_probe()
1061 lane->id = val; in mvebu_comphy_probe()
1062 lane->port = -1; in mvebu_comphy_probe()
1063 phy_set_drvdata(phy, lane); in mvebu_comphy_probe()
1069 * reasons we cannot de-configure the COMPHY without being sure in mvebu_comphy_probe()
1070 * that the firmware is up-to-date and fully-featured. in mvebu_comphy_probe()
1074 dev_set_drvdata(&pdev->dev, priv); in mvebu_comphy_probe()
1075 provider = devm_of_phy_provider_register(&pdev->dev, in mvebu_comphy_probe()
1087 { .compatible = "marvell,comphy-cp110" },
1095 .name = "mvebu-comphy",
1101 MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");