1Qualcomm Camera Subsystem
2
3* Properties
4
5- compatible:
6	Usage: required
7	Value type: <stringlist>
8	Definition: Should contain one of:
9		- "qcom,msm8916-camss"
10		- "qcom,msm8996-camss"
11- reg:
12	Usage: required
13	Value type: <prop-encoded-array>
14	Definition: Register ranges as listed in the reg-names property.
15- reg-names:
16	Usage: required
17	Value type: <stringlist>
18	Definition: Should contain the following entries:
19		- "csiphy0"
20		- "csiphy0_clk_mux"
21		- "csiphy1"
22		- "csiphy1_clk_mux"
23		- "csiphy2"		(8996 only)
24		- "csiphy2_clk_mux"	(8996 only)
25		- "csid0"
26		- "csid1"
27		- "csid2"		(8996 only)
28		- "csid3"		(8996 only)
29		- "ispif"
30		- "csi_clk_mux"
31		- "vfe0"
32		- "vfe1"		(8996 only)
33- interrupts:
34	Usage: required
35	Value type: <prop-encoded-array>
36	Definition: Interrupts as listed in the interrupt-names property.
37- interrupt-names:
38	Usage: required
39	Value type: <stringlist>
40	Definition: Should contain the following entries:
41		- "csiphy0"
42		- "csiphy1"
43		- "csiphy2"		(8996 only)
44		- "csid0"
45		- "csid1"
46		- "csid2"		(8996 only)
47		- "csid3"		(8996 only)
48		- "ispif"
49		- "vfe0"
50		- "vfe1"		(8996 only)
51- power-domains:
52	Usage: required
53	Value type: <prop-encoded-array>
54	Definition: A phandle and power domain specifier pairs to the
55		    power domain which is responsible for collapsing
56		    and restoring power to the peripheral.
57- clocks:
58	Usage: required
59	Value type: <prop-encoded-array>
60	Definition: A list of phandle and clock specifier pairs as listed
61		    in clock-names property.
62- clock-names:
63	Usage: required
64	Value type: <stringlist>
65	Definition: Should contain the following entries:
66		- "top_ahb"
67		- "ispif_ahb"
68		- "csiphy0_timer"
69		- "csiphy1_timer"
70		- "csiphy2_timer"	(8996 only)
71		- "csi0_ahb"
72		- "csi0"
73		- "csi0_phy"
74		- "csi0_pix"
75		- "csi0_rdi"
76		- "csi1_ahb"
77		- "csi1"
78		- "csi1_phy"
79		- "csi1_pix"
80		- "csi1_rdi"
81		- "csi2_ahb"		(8996 only)
82		- "csi2"		(8996 only)
83		- "csi2_phy"		(8996 only)
84		- "csi2_pix"		(8996 only)
85		- "csi2_rdi"		(8996 only)
86		- "csi3_ahb"		(8996 only)
87		- "csi3"		(8996 only)
88		- "csi3_phy"		(8996 only)
89		- "csi3_pix"		(8996 only)
90		- "csi3_rdi"		(8996 only)
91		- "ahb"
92		- "vfe0"
93		- "csi_vfe0"
94		- "vfe0_ahb",		(8996 only)
95		- "vfe0_stream",	(8996 only)
96		- "vfe1",		(8996 only)
97		- "csi_vfe1",		(8996 only)
98		- "vfe1_ahb",		(8996 only)
99		- "vfe1_stream",	(8996 only)
100		- "vfe_ahb"
101		- "vfe_axi"
102- vdda-supply:
103	Usage: required
104	Value type: <phandle>
105	Definition: A phandle to voltage supply for CSI2.
106- iommus:
107	Usage: required
108	Value type: <prop-encoded-array>
109	Definition: A list of phandle and IOMMU specifier pairs.
110
111* Nodes
112
113- ports:
114	Usage: required
115	Definition: As described in video-interfaces.txt in same directory.
116	Properties:
117		- reg:
118			Usage: required
119			Value type: <u32>
120			Definition: Selects CSI2 PHY interface - PHY0, PHY1
121				    or PHY2 (8996 only)
122	Endpoint node properties:
123		- clock-lanes:
124			Usage: required
125			Value type: <u32>
126			Definition: The physical clock lane index. On 8916
127				    the value must always be <1> as the physical
128				    clock lane is lane 1. On 8996 the value must
129				    always be <7> as the hardware supports D-PHY
130				    and C-PHY, indexes are in a common set and
131				    D-PHY physical clock lane is labeled as 7.
132		- data-lanes:
133			Usage: required
134			Value type: <prop-encoded-array>
135			Definition: An array of physical data lanes indexes.
136				    Position of an entry determines the logical
137				    lane number, while the value of an entry
138				    indicates physical lane index. Lane swapping
139				    is supported. Physical lane indexes for
140				    8916: 0, 2, 3, 4; for 8996: 0, 1, 2, 3.
141
142* An Example
143
144	camss: camss@1b00000 {
145		compatible = "qcom,msm8916-camss";
146		reg = <0x1b0ac00 0x200>,
147			<0x1b00030 0x4>,
148			<0x1b0b000 0x200>,
149			<0x1b00038 0x4>,
150			<0x1b08000 0x100>,
151			<0x1b08400 0x100>,
152			<0x1b0a000 0x500>,
153			<0x1b00020 0x10>,
154			<0x1b10000 0x1000>;
155		reg-names = "csiphy0",
156			"csiphy0_clk_mux",
157			"csiphy1",
158			"csiphy1_clk_mux",
159			"csid0",
160			"csid1",
161			"ispif",
162			"csi_clk_mux",
163			"vfe0";
164		interrupts = <GIC_SPI 78 0>,
165			<GIC_SPI 79 0>,
166			<GIC_SPI 51 0>,
167			<GIC_SPI 52 0>,
168			<GIC_SPI 55 0>,
169			<GIC_SPI 57 0>;
170		interrupt-names = "csiphy0",
171			"csiphy1",
172			"csid0",
173			"csid1",
174			"ispif",
175			"vfe0";
176		power-domains = <&gcc VFE_GDSC>;
177		clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
178			<&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
179			<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
180			<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
181			<&gcc GCC_CAMSS_CSI0_AHB_CLK>,
182			<&gcc GCC_CAMSS_CSI0_CLK>,
183			<&gcc GCC_CAMSS_CSI0PHY_CLK>,
184			<&gcc GCC_CAMSS_CSI0PIX_CLK>,
185			<&gcc GCC_CAMSS_CSI0RDI_CLK>,
186			<&gcc GCC_CAMSS_CSI1_AHB_CLK>,
187			<&gcc GCC_CAMSS_CSI1_CLK>,
188			<&gcc GCC_CAMSS_CSI1PHY_CLK>,
189			<&gcc GCC_CAMSS_CSI1PIX_CLK>,
190			<&gcc GCC_CAMSS_CSI1RDI_CLK>,
191			<&gcc GCC_CAMSS_AHB_CLK>,
192			<&gcc GCC_CAMSS_VFE0_CLK>,
193			<&gcc GCC_CAMSS_CSI_VFE0_CLK>,
194			<&gcc GCC_CAMSS_VFE_AHB_CLK>,
195			<&gcc GCC_CAMSS_VFE_AXI_CLK>;
196		clock-names = "top_ahb",
197			"ispif_ahb",
198			"csiphy0_timer",
199			"csiphy1_timer",
200			"csi0_ahb",
201			"csi0",
202			"csi0_phy",
203			"csi0_pix",
204			"csi0_rdi",
205			"csi1_ahb",
206			"csi1",
207			"csi1_phy",
208			"csi1_pix",
209			"csi1_rdi",
210			"ahb",
211			"vfe0",
212			"csi_vfe0",
213			"vfe_ahb",
214			"vfe_axi";
215		vdda-supply = <&pm8916_l2>;
216		iommus = <&apps_iommu 3>;
217		ports {
218			#address-cells = <1>;
219			#size-cells = <0>;
220			port@0 {
221				reg = <0>;
222				csiphy0_ep: endpoint {
223					clock-lanes = <1>;
224					data-lanes = <0 2>;
225					remote-endpoint = <&ov5645_ep>;
226				};
227			};
228		};
229	};
230