| /Linux-v6.1/drivers/phy/marvell/ |
| D | phy-mvebu-cp110-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
19 /* Relative to priv->base */
21 #define MVEBU_COMPHY_SERDES_CFG0_PU_PLL BIT(1)
51 #define MVEBU_COMPHY_GEN1_S0_TX_AMP(n) ((n) << 1)
64 #define MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(n) ((n) << 1)
107 /* Relative to priv->regmap */
109 #define MVEBU_COMPHY_CONF1_PWRUP BIT(1)
128 * A lane is described by the following bitfields:
[all …]
|
| D | phy-mvebu-a3700-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
39 * When accessing common PHY lane registers directly, we need to shift by 1,
40 * since the registers are 16-bit.
42 #define COMPHY_LANE_REG_DIRECT(reg) (((reg) & 0x7FF) << 1)
128 #define PRD_TXMARGIN_MASK GENMASK(3, 1)
148 #define PIPE_REG_RESET BIT(1)
159 #define BUNDLE_PERIOD_SEL BIT(1)
174 * This register is not from PHY lane register space. It only exists in the
175 * indirect register space, before the actual PHY lane 2 registers. So the
[all …]
|
| D | phy-armada38x-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
46 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
58 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
60 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
63 if (priv->conf) { in a38x_set_conf()
64 conf = readl_relaxed(priv->conf); in a38x_set_conf()
66 conf |= BIT(lane->port); in a38x_set_conf()
68 conf &= ~BIT(lane->port); in a38x_set_conf()
69 writel(conf, priv->conf); in a38x_set_conf()
73 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, in a38x_comphy_set_reg() argument
[all …]
|
| /Linux-v6.1/drivers/net/dsa/b53/ |
| D | b53_serdes.c | 1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
42 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
50 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
54 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
57 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
61 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
64 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
[all …]
|
| /Linux-v6.1/drivers/phy/tegra/ |
| D | xusb-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only
39 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 4) + 3))
46 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
47 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
48 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
49 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4))
51 (1 << (17 + (x) * 4))
52 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4))
55 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
57 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
[all …]
|
| D | xusb-tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
51 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
65 USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
67 SS_PORT_WAKEUP_EVENT(0) | SS_PORT_WAKEUP_EVENT(1) | \
72 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
73 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
74 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29)
75 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
[all …]
|
| D | xusb-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
35 #define PORT_XUSB 1
57 (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
64 #define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3)
94 #define HSIC_PD_TX_DATA0 BIT(1)
123 #define CAP_CFG BIT(1)
134 #define UTMI_FS SPEED(1)
[all …]
|
| /Linux-v6.1/drivers/net/dsa/mv88e6xxx/ |
| D | serdes.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
37 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument
41 return mv88e6xxx_phy_read(chip, lane, reg_c45, val); in mv88e6390_serdes_read()
45 int lane, int device, int reg, u16 val) in mv88e6390_serdes_write() argument
49 return mv88e6xxx_phy_write(chip, lane, reg_c45, val); in mv88e6390_serdes_write()
56 state->link = false; in mv88e6xxx_serdes_pcs_get_state()
64 state->link = !!(status & MV88E6390_SGMII_PHY_STATUS_LINK); in mv88e6xxx_serdes_pcs_get_state()
65 state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE); in mv88e6xxx_serdes_pcs_get_state()
68 /* The Spped and Duplex Resolved register is 1 if AN is enabled in mv88e6xxx_serdes_pcs_get_state()
72 state->duplex = status & in mv88e6xxx_serdes_pcs_get_state()
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/media/ |
| D | video-interfaces.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
29 #address-cells = <1>;
30 #size-cells = <0>;
35 endpoint@1 { ... };
37 port@1 { ... };
[all …]
|
| /Linux-v6.1/drivers/phy/ |
| D | phy-xgene.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
[all …]
|
| /Linux-v6.1/sound/soc/tegra/ |
| D | tegra186_asrc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra186_asrc.c - Tegra186 ASRC driver
32 (((id) + 1) << 4) }, \
46 ASRC_STREAM_REG_DEFAULTS(1),
74 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
77 1); in tegra186_asrc_lock_stream()
84 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
85 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
95 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
102 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
[all …]
|
| /Linux-v6.1/drivers/thunderbolt/ |
| D | lc.c | 1 // SPDX-License-Identifier: GPL-2.0
12 * tb_lc_read_uuid() - Read switch UUID from link controller common register
18 if (!sw->cap_lc) in tb_lc_read_uuid()
19 return -EINVAL; in tb_lc_read_uuid()
20 return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4); in tb_lc_read_uuid()
25 if (!sw->cap_lc) in read_lc_desc()
26 return -EINVAL; in read_lc_desc()
27 return tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1); in read_lc_desc()
32 struct tb_switch *sw = port->sw; in find_port_lc_cap()
43 phys = tb_phy_port_from_link(port->port); in find_port_lc_cap()
[all …]
|
| /Linux-v6.1/drivers/gpu/drm/bridge/analogix/ |
| D | analogix_dp_core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
83 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd()
85 if (!dp->force_hpd) in analogix_dp_detect_hpd()
86 return -ETIMEDOUT; in analogix_dp_detect_hpd()
93 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd()
98 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd()
99 return -EINVAL; in analogix_dp_detect_hpd()
102 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd()
112 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr()
113 if (ret != 1) { in analogix_dp_detect_sink_psr()
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/media/i2c/ |
| D | st,st-mipid02.txt | 1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
[all …]
|
| /Linux-v6.1/drivers/phy/xilinx/ |
| D | phy-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
29 * Lane Registers
32 /* TX De-emphasis parameters */
45 #define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1)
138 #define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2)
151 #define XPSGTR_TYPE_USB1 1 /* USB controller 1 */
152 #define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
[all …]
|
| /Linux-v6.1/drivers/phy/freescale/ |
| D | phy-fsl-lynx-28g.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2021-2022 NXP. */
23 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
44 /* Per SerDes lane registers */
45 /* Lane a General Control Register */
46 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
54 /* Lane a Tx Reset Control Register */
55 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
60 /* Lane a Tx General Control Register */
61 #define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24) argument
[all …]
|
| /Linux-v6.1/drivers/media/platform/ti/omap3isp/ |
| D | omap3isp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
26 * @data_lane_shift: Data lane shifter
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
[all …]
|
| /Linux-v6.1/drivers/gpu/drm/i915/display/ |
| D | intel_dp_link_training.c | 2 * Copyright © 2008-2015 Intel Corporation
31 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); in intel_dp_reset_lttpr_common_caps()
36 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - in intel_dp_reset_lttpr_count()
43 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; in intel_dp_lttpr_phy_caps()
50 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_dp_read_lttpr_phy_caps()
53 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { in intel_dp_read_lttpr_phy_caps()
54 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, in intel_dp_read_lttpr_phy_caps()
56 encoder->base.base.id, encoder->base.name, in intel_dp_read_lttpr_phy_caps()
61 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, in intel_dp_read_lttpr_phy_caps()
63 encoder->base.base.id, encoder->base.name, in intel_dp_read_lttpr_phy_caps()
[all …]
|
| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_dp.c | 50 link->ctx->logger
133 link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_cr_training_aux_rd_interval()
160 link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_eq_training_aux_rd_interval()
170 case 1: return 4000; in get_eq_training_aux_rd_interval()
251 1); in dpcd_set_training_pattern()
276 struct dpcd_caps *rx_caps = &link->dpcd_caps; in decide_eq_training_pattern()
281 enc_caps = &link_enc->features; in decide_eq_training_pattern()
285 if (enc_caps->flags.bits.IS_TPS4_CAPABLE && in decide_eq_training_pattern()
286 rx_caps->max_down_spread.bits.TPS4_SUPPORTED) in decide_eq_training_pattern()
288 else if (enc_caps->flags.bits.IS_TPS3_CAPABLE && in decide_eq_training_pattern()
[all …]
|
| /Linux-v6.1/drivers/net/ethernet/ti/ |
| D | netcp_xgbepcsr.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * WingMan Kwok <w-kwok2@ti.com>
17 /* PCS-R registers */
26 #define MASK_WID_SH(w, s) (((1 << w) - 1) << s)
146 /* lane is 0 based */
148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
152 /* lane setup */ in netcp_xgbe_serdes_lane_config()
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
[all …]
|
| /Linux-v6.1/include/linux/phy/ |
| D | phy-dp.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
31 * lane 0, used for the transmissions on main link.
33 * Allowed values: 1, 2, 4
41 * to be used by particular lanes. One value per lane.
42 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
51 * Pre-emphasis levels, as specified by DisplayPort specification, to be
52 * used by particular lanes. One value per lane.
61 * Flag indicating, whether or not to enable spread-spectrum clocking.
64 u8 ssc : 1;
[all …]
|
| /Linux-v6.1/drivers/pinctrl/tegra/ |
| D | pinctrl-tegra-xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
20 #include "../pinctrl-utils.h"
23 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
24 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
25 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
28 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
30 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
33 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
34 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/phy/ |
| D | phy-mvebu-comphy.txt | 2 --------------------
12 - compatible: should be one of:
13 * "marvell,comphy-cp110" for Armada 7k/8k
14 * "marvell,comphy-a3700" for Armada 3700
15 - reg: should contain the COMPHY register(s) location(s) and length(s).
16 * 1 entry for Armada 7k/8k
17 * 4 entries for Armada 3700 along with the corresponding reg-names
20 * Lane 1 (PCIe/GbE)
21 * Lane 0 (USB3/GbE)
22 * Lane 2 (SATA/USB3)
[all …]
|
| /Linux-v6.1/drivers/phy/rockchip/ |
| D | phy-rockchip-typec.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
5 * Kever Yang <kever.yang@rock-chips.com>
7 * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock
8 * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has
19 * 1. USB3 only mode:
34 * This Type-C PHY driver supports normal and flip orientation. The orientation
40 #include <linux/clk-provider.h>
126 #define CMN_CALIB_CODE_POS_MASK GENMASK(CMN_CALIB_CODE_WIDTH - 1, 0)
204 #define TXDA_DRV_IDLE_LOWI_EN BIT(1)
[all …]
|
| /Linux-v6.1/drivers/net/ethernet/sfc/falcon/ |
| D | txc43128_phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
24 #define TXC_LOOPBACKS ((1 << LOOPBACK_PCS) | \
25 (1 << LOOPBACK_PMAPMD) | \
26 (1 << LOOPBACK_PHYXS_WS))
30 * Compile-time config
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
63 /* Lane selection */
[all …]
|
