Lines Matching +full:1 +full:- +full:lane
2 --------------------
12 - compatible: should be one of:
13 * "marvell,comphy-cp110" for Armada 7k/8k
14 * "marvell,comphy-a3700" for Armada 3700
15 - reg: should contain the COMPHY register(s) location(s) and length(s).
16 * 1 entry for Armada 7k/8k
17 * 4 entries for Armada 3700 along with the corresponding reg-names
20 * Lane 1 (PCIe/GbE)
21 * Lane 0 (USB3/GbE)
22 * Lane 2 (SATA/USB3)
23 - marvell,system-controller: should contain a phandle to the system
25 - #address-cells: should be 1.
26 - #size-cells: should be 0.
30 - clocks: pointers to the reference clocks for this device (CP110 only),
32 - clock-names: names of used clocks for CP110 only, must be :
35 A sub-node is required for each comphy lane provided by the comphy.
39 - reg: COMPHY lane number.
40 - #phy-cells : from the generic PHY bindings, must be 1. Defines the
41 input port to use for a given comphy lane.
46 compatible = "marvell,comphy-cp110";
48 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
49 clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
50 <&CP11X_LABEL(clk) 1 18>;
51 clock-names = "mg_clk", "mg_core_clk", "axi_clk";
52 #address-cells = <1>;
53 #size-cells = <0>;
57 #phy-cells = <1>;
60 CP11X_LABEL(comphy1): phy@1 {
61 reg = <1>;
62 #phy-cells = <1>;
67 compatible = "marvell,comphy-a3700";
72 reg-names = "comphy",
76 #address-cells = <1>;
77 #size-cells = <0>;
82 #phy-cells = <1>;
85 comphy1: phy@1 {
86 reg = <1>;
87 #phy-cells = <1>;
92 #phy-cells = <1>;