Home
last modified time | relevance | path

Searched +full:0 +full:xe1000000 (Results 1 – 21 of 21) sorted by relevance

/Linux-v5.15/arch/arm/mach-omap1/include/mach/
Domap7xx.h40 #define OMAP7XX_DSP_BASE 0xE0000000
41 #define OMAP7XX_DSP_SIZE 0x50000
42 #define OMAP7XX_DSP_START 0xE0000000
44 #define OMAP7XX_DSPREG_BASE 0xE1000000
46 #define OMAP7XX_DSPREG_START 0xE1000000
48 #define OMAP7XX_SPI1_BASE 0xfffc0800
49 #define OMAP7XX_SPI2_BASE 0xfffc1000
56 #define OMAP7XX_CONFIG_BASE 0xfffe1000
57 #define OMAP7XX_IO_CONF_0 0xfffe1070
58 #define OMAP7XX_IO_CONF_1 0xfffe1074
[all …]
Domap1510.h38 #define OMAP1510_DSP_BASE 0xE0000000
39 #define OMAP1510_DSP_SIZE 0x28000
40 #define OMAP1510_DSP_START 0xE0000000
42 #define OMAP1510_DSPREG_BASE 0xE1000000
44 #define OMAP1510_DSPREG_START 0xE1000000
46 #define OMAP1510_DSP_MMU_BASE (0xfffed200)
53 #define OMAP1510_FPGA_BASE 0xE8000000 /* VA */
55 #define OMAP1510_FPGA_START 0x08000000 /* PA */
58 #define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0)
59 #define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1)
[all …]
Domap16xx.h38 #define OMAP16XX_DSP_BASE 0xE0000000
39 #define OMAP16XX_DSP_SIZE 0x28000
40 #define OMAP16XX_DSP_START 0xE0000000
42 #define OMAP16XX_DSPREG_BASE 0xE1000000
44 #define OMAP16XX_DSPREG_START 0xE1000000
46 #define OMAP16XX_SEC_BASE 0xFFFE4000
47 #define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
48 #define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
49 #define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
56 #define OMAP_IH2_0_BASE (0xfffe0000)
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/mtd/
Darm,pl353-nand-r2p1.yaml38 reg = <0xe000e000 0x0001000>;
41 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
42 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
43 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
47 nfc0: nand-controller@0,0 {
49 reg = <0 0 0x1000000>;
51 #size-cells = <0>;
Dintel,lgm-nand.yaml46 const: 0
53 minimum: 0
79 reg = <0xe0f00000 0x100>,
80 <0xe1000000 0x300>,
81 <0xe1400000 0x8000>,
82 <0xe1c00000 0x1000>,
83 <0x17400000 0x4>,
84 <0x17c00000 0x4>;
91 #size-cells = <0>;
93 nand@0 {
[all …]
/Linux-v5.15/include/video/
Dcvisionppc.h27 #define CSPPC_PCI_BRIDGE 0xfffe0000
28 #define CSPPC_BRIDGE_ENDIAN 0x0000
29 #define CSPPC_BRIDGE_INT 0x0010
31 #define CVPPC_PCI_CONFIG 0xfffc0000
32 #define CVPPC_ROM_ADDRESS 0xe2000001
33 #define CVPPC_REGS_REGION 0xef000000
34 #define CVPPC_FB_APERTURE_ONE 0xe0000000
35 #define CVPPC_FB_APERTURE_TWO 0xe1000000
36 #define CVPPC_FB_SIZE 0x00800000
37 #define CVPPC_MEM_CONFIG_OLD 0xed61fcaa /* FIXME Fujitsu?? */
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/fsl/
Dmpc8544ds.dts16 reg = <0 0 0 0>; // Filled by U-Boot
20 reg = <0 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0x0 0xff800000 0x800000>;
26 ranges = <0x0 0x0 0xe0000000 0x100000>;
30 reg = <0 0xe0008000 0 0x1000>;
31 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
34 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
37 /* IDSEL 0x11 J17 Slot 1 */
38 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/
Darm,pl353-smc.yaml29 pattern: "^memory-controller@[0-9a-f]+$"
63 <cs-number> 0 <offset> <size>
65 - description: NAND bank 0
66 - description: NOR/SRAM bank 0
72 "@[0-3],[a-f0-9]+$":
89 minimum: 0
115 reg = <0xe000e000 0x0001000>;
118 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
119 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
120 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
[all …]
/Linux-v5.15/arch/arm64/boot/dts/amd/
Damd-seattle-soc.dtsi20 reg = <0x0 0xe1110000 0 0x1000>,
21 <0x0 0xe112f000 0 0x2000>,
22 <0x0 0xe1140000 0 0x2000>,
23 <0x0 0xe1160000 0 0x2000>;
24 interrupts = <1 9 0xf04>;
25 ranges = <0 0 0 0xe1100000 0 0x100000>;
29 reg = <0x0 0x00080000 0 0x1000>;
35 interrupts = <1 13 0xff04>,
36 <1 14 0xff04>,
37 <1 11 0xff04>,
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/
Dcurrituck.dts13 /memreserve/ 0x01f00000 0x00100000; // spin table
20 dcr-parent = <&{/cpus/cpu@0}>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
58 cpu-release-addr = <0x0 0x01f00000>;
64 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
70 dcr-reg = <0xffc00000 0x00040000>;
71 #address-cells = <0>;
72 #size-cells = <0>;
[all …]
Dmpc8610_hpcd.dts26 #size-cells = <0>;
28 PowerPC,8610@0 {
30 reg = <0>;
35 sleep = <&pmc 0x00008000 0 // core
36 &pmc 0x00004000 0>; // timebase
37 timebase-frequency = <0>; // From uboot
38 bus-frequency = <0>; // From uboot
39 clock-frequency = <0>; // From uboot
45 reg = <0x00000000 0x20000000>; // 512M at 0x0
52 reg = <0xe0005000 0x1000>;
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
Dzynq-7000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0>;
47 interrupts = <0 5 4>, <0 6 4>;
49 reg = <0xf8891000 0x1000>,
50 <0xf8893000 0x1000>;
69 #size-cells = <0>;
72 port@0 {
73 reg = <0>;
104 reg = <0xf8007100 0x20>;
[all …]
/Linux-v5.15/arch/arm/mach-cns3xxx/
Dcns3xxx.h12 #define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */
15 #define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */
17 #define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */
19 #define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */
21 #define CNS3XXX_PPE_BASE 0x70001000 /* HANT */
23 #define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */
25 #define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */
27 #define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */
29 #define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */
31 #define SMC_MEMC_STATUS_OFFSET 0x000
[all …]
/Linux-v5.15/arch/arm/mach-lpc32xx/
Dlpc32xx.h17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
[all …]
/Linux-v5.15/crypto/
Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/Linux-v5.15/drivers/scsi/sym53c8xx_2/
Dsym_defs.h45 #define FE_LED0 (1<<0)
88 #define ISCON 0x10 /* connected to scsi */
89 #define CRST 0x08 /* force reset */
90 #define IARB 0x02 /* immediate arbitration */
93 #define SDU 0x80 /* cmd: disconnect will raise error */
94 #define CHM 0x40 /* sta: chained mode */
95 #define WSS 0x08 /* sta: wide scsi send [W]*/
96 #define WSR 0x01 /* sta: wide scsi received [W]*/
99 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
100 #define ULTRA 0x80 /* cmd: ULTRA enable */
[all …]
/Linux-v5.15/drivers/net/ethernet/dec/tulip/
Duli526x.c39 #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
40 #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
42 #define ULI526X_IO_SIZE 0x100
43 #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
44 #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
48 #define TX_BUF_ALLOC 0x600
49 #define RX_ALLOC_SIZE 0x620
51 #define CR0_DEFAULT 0
52 #define CR6_DEFAULT 0x22200000
53 #define CR7_DEFAULT 0x180c1
[all …]
Ddmfe.c22 Removed IRQ 0-15 assumption
92 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
93 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
94 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
95 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
97 #define DM9102_IO_SIZE 0x80
98 #define DM9102A_IO_SIZE 0x100
99 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
100 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
101 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
[all …]
/Linux-v5.15/drivers/scsi/
Dncr53c8xx.h72 * bit 0 : all features enabled, except:
107 #define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
128 #if CONFIG_SCSI_NCR53C8XX_SYNC == 0
146 #define SCSI_NCR_SETUP_DISCONNECTION (0)
157 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0)
164 #define SCSI_NCR_SETUP_MASTER_PARITY (0)
173 #define SCSI_NCR_SETUP_SCSI_PARITY (0)
410 …np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0)
446 } while (0)
452 } while (0)
[all …]
/Linux-v5.15/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_hsi.h17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
25 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
33 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
42 #define PIN_CFG_NA 0x00000000
43 #define PIN_CFG_GPIO0_P0 0x00000001
44 #define PIN_CFG_GPIO1_P0 0x00000002
[all …]