Lines Matching +full:0 +full:xe1000000
22 Removed IRQ 0-15 assumption
92 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
93 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
94 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
95 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
97 #define DM9102_IO_SIZE 0x80
98 #define DM9102A_IO_SIZE 0x100
99 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
100 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
101 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
105 #define TX_BUF_ALLOC 0x600
106 #define RX_ALLOC_SIZE 0x620
108 #define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
109 #define CR6_DEFAULT 0x00080000 /* HD */
110 #define CR7_DEFAULT 0x180c1
111 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
112 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
116 #define MAX_CHECK_PACKET 0x8000
120 #define DMFE_WOL_LINKCHANGE 0x20000000
121 #define DMFE_WOL_SAMPLEPACKET 0x10000000
122 #define DMFE_WOL_MAGICPACKET 0x08000000
125 #define DMFE_10MHF 0
130 #define DMFE_1M_HPNA 0x10
132 #define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
133 #define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
134 #define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
135 #define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
136 #define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
137 #define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
154 } while (0)
163 #define CR9_SROM_READ 0x4800
164 #define CR9_SRCS 0x1
165 #define CR9_SRCLK 0x2
166 #define CR9_CRDOUT 0x8
167 #define SROM_DATA_0 0x0
168 #define SROM_DATA_1 0x4
169 #define PHY_DATA_1 0x20000
170 #define PHY_DATA_0 0x00000
171 #define MDCLKH 0x10000
173 #define PHY_POWER_DOWN 0x800
175 #define SROM_V41_CODE 0x14
178 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
240 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
268 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
269 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
270 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
271 DCR15 = 0x78
275 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
276 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
277 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
359 DMFE_DBUG(0, "dmfe_init_one()", 0); in dmfe_init_one()
366 if ((ent->driver_data == PCI_DM9100_ID && pdev->revision >= 0x30) || in dmfe_init_one()
394 if (!pci_resource_start(pdev, 0)) { in dmfe_init_one()
400 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) { in dmfe_init_one()
406 #if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */ in dmfe_init_one()
412 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); in dmfe_init_one()
426 sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, in dmfe_init_one()
448 db->ioaddr = pci_iomap(pdev, 0, 0); in dmfe_init_one()
455 db->wol_mode = 0; in dmfe_init_one()
465 pci_read_config_dword(pdev, 0x50, &pci_pmr); in dmfe_init_one()
466 pci_pmr &= 0x70000; in dmfe_init_one()
467 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) ) in dmfe_init_one()
470 db->chip_type = 0; in dmfe_init_one()
473 for (i = 0; i < 64; i++) { in dmfe_init_one()
479 for (i = 0; i < 6; i++) in dmfe_init_one()
492 return 0; in dmfe_init_one()
501 sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, in dmfe_init_one()
519 DMFE_DBUG(0, "dmfe_remove_one()", 0); in dmfe_remove_one()
526 sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, in dmfe_remove_one()
535 DMFE_DBUG(0, "dmfe_remove_one() exit", 0); in dmfe_remove_one()
550 DMFE_DBUG(0, "dmfe_open", 0); in dmfe_open()
558 db->tx_packet_cnt = 0; in dmfe_open()
559 db->tx_queue_cnt = 0; in dmfe_open()
560 db->rx_avail_cnt = 0; in dmfe_open()
561 db->wait_reset = 0; in dmfe_open()
563 db->first_in_callback = 0; in dmfe_open()
564 db->NIC_capability = 0xf; /* All capability*/ in dmfe_open()
565 db->PHY_reg4 = 0x1e0; in dmfe_open()
569 (db->chip_revision >= 0x30) ) { in dmfe_open()
575 db->cr0_data = 0; in dmfe_open()
586 timer_setup(&db->timer, dmfe_timer, 0); in dmfe_open()
590 return 0; in dmfe_open()
606 DMFE_DBUG(0, "dmfe_init_dm910x()", 0); in dmfe_init_dm910x()
622 dw32(DCR12, 0x180); /* Let bit 7 output port */ in dmfe_init_dm910x()
624 dw32(DCR12, 0x80); /* Issue RESET signal */ in dmfe_init_dm910x()
627 dw32(DCR12, 0x0); /* Clear RESET signal */ in dmfe_init_dm910x()
630 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */ in dmfe_init_dm910x()
657 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000; in dmfe_init_dm910x()
675 DMFE_DBUG(0, "dmfe_start_xmit", 0); in dmfe_start_xmit()
697 dw32(DCR7, 0); in dmfe_start_xmit()
702 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len); in dmfe_start_xmit()
709 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */ in dmfe_start_xmit()
711 dw32(DCR1, 0x1); /* Issue Tx polling */ in dmfe_start_xmit()
715 dw32(DCR1, 0x1); /* Issue Tx polling */ in dmfe_start_xmit()
743 DMFE_DBUG(0, "dmfe_stop", 0); in dmfe_stop()
754 dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); in dmfe_stop()
762 #if 0 in dmfe_stop()
771 return 0; in dmfe_stop()
787 DMFE_DBUG(0, "dmfe_interrupt()", 0); in dmfe_interrupt()
794 if ( !(db->cr5_data & 0xc1) ) { in dmfe_interrupt()
800 dw32(DCR7, 0); in dmfe_interrupt()
803 if (db->cr5_data & 0x2000) { in dmfe_interrupt()
813 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt ) in dmfe_interrupt()
821 if ( db->cr5_data & 0x01) in dmfe_interrupt()
825 if (db->dm910x_chk_mode & 0x2) { in dmfe_interrupt()
826 db->dm910x_chk_mode = 0x4; in dmfe_interrupt()
827 db->cr6_data |= 0x100; in dmfe_interrupt()
872 if (tdes0 & 0x80000000) in dmfe_free_tx_pkt()
880 if ( tdes0 != 0x7fffffff ) { in dmfe_free_tx_pkt()
881 dev->stats.collisions += (tdes0 >> 3) & 0xf; in dmfe_free_tx_pkt()
882 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff; in dmfe_free_tx_pkt()
886 if (tdes0 & 0x0002) { /* UnderRun */ in dmfe_free_tx_pkt()
893 if (tdes0 & 0x0100) in dmfe_free_tx_pkt()
895 if (tdes0 & 0x0200) in dmfe_free_tx_pkt()
897 if (tdes0 & 0x0400) in dmfe_free_tx_pkt()
899 if (tdes0 & 0x0800) in dmfe_free_tx_pkt()
901 if (tdes0 & 0x4000) in dmfe_free_tx_pkt()
914 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */ in dmfe_free_tx_pkt()
917 dw32(DCR1, 0x1); /* Issue Tx polling */ in dmfe_free_tx_pkt()
930 * 0 : return the normal CRC (for Hash Table index)
935 u32 crc = crc32(~0, Data, Len); in cal_CRC()
956 if (rdes0 & 0x80000000) /* packet owner check */ in dmfe_rx_packet()
965 if ( (rdes0 & 0x300) != 0x300) { in dmfe_rx_packet()
968 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0); in dmfe_rx_packet()
972 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4; in dmfe_rx_packet()
975 if (rdes0 & 0x8000) { in dmfe_rx_packet()
982 if (rdes0 & 0x80) in dmfe_rx_packet()
986 if ( !(rdes0 & 0x8000) || in dmfe_rx_packet()
1021 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0); in dmfe_rx_packet()
1042 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0); in dmfe_set_filter_mode()
1046 DMFE_DBUG(0, "Enable PROM Mode", 0); in dmfe_set_filter_mode()
1054 DMFE_DBUG(0, "Pass all multicast address", mc_count); in dmfe_set_filter_mode()
1061 DMFE_DBUG(0, "Set multicast address", mc_count); in dmfe_set_filter_mode()
1092 return 0; in dmfe_ethtool_set_wol()
1128 DMFE_DBUG(0, "dmfe_timer()", 0); in dmfe_timer()
1132 if (db->first_in_callback == 0) { in dmfe_timer()
1135 db->cr6_data &= ~0x40000; in dmfe_timer()
1137 dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x1000, db->chip_id); in dmfe_timer()
1138 db->cr6_data |= 0x40000; in dmfe_timer()
1149 if ( (db->dm910x_chk_mode & 0x1) && in dmfe_timer()
1151 db->dm910x_chk_mode = 0x4; in dmfe_timer()
1155 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) { in dmfe_timer()
1159 db->interval_rx_cnt = 0; in dmfe_timer()
1164 dw32(DCR1, 0x1); /* Tx polling again */ in dmfe_timer()
1175 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt); in dmfe_timer()
1178 db->first_in_callback = 0; in dmfe_timer()
1192 (db->chip_revision == 0x30)) || in dmfe_timer()
1194 (db->chip_revision == 0x10)) ) { in dmfe_timer()
1197 link_ok = 0; in dmfe_timer()
1202 /*0x43 is used instead of 0x3 because bit 6 should represent in dmfe_timer()
1204 link_ok = (tmp_cr12 & 0x43) ? 1 : 0; in dmfe_timer()
1215 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0; in dmfe_timer()
1218 DMFE_DBUG (0, "PHY and chip report different link status", 0); in dmfe_timer()
1224 DMFE_DBUG(0, "Link Failed", tmp_cr12); in dmfe_timer()
1229 if ( !(db->media_mode & 0x38) ) in dmfe_timer()
1231 0, 0x1000, db->chip_id); in dmfe_timer()
1236 db->cr6_data|=0x00040000; /* bit18=1, MII */ in dmfe_timer()
1237 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */ in dmfe_timer()
1242 DMFE_DBUG(0, "Link link OK", tmp_cr12); in dmfe_timer()
1254 if (db->HPNA_command & 0xf00) { in dmfe_timer()
1280 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0); in dmfe_dynamic_reset()
1285 dw32(DCR7, 0); /* Disable Interrupt */ in dmfe_dynamic_reset()
1295 db->tx_packet_cnt = 0; in dmfe_dynamic_reset()
1296 db->tx_queue_cnt = 0; in dmfe_dynamic_reset()
1297 db->rx_avail_cnt = 0; in dmfe_dynamic_reset()
1299 db->wait_reset = 0; in dmfe_dynamic_reset()
1315 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0); in dmfe_free_rxbuffer()
1334 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) { in dmfe_reuse_skb()
1339 rxptr->rdes0 = cpu_to_le32(0x80000000); in dmfe_reuse_skb()
1343 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt); in dmfe_reuse_skb()
1363 DMFE_DBUG(0, "dmfe_descriptor_init()", 0); in dmfe_descriptor_init()
1384 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) { in dmfe_descriptor_init()
1386 tmp_tx->tdes0 = cpu_to_le32(0); in dmfe_descriptor_init()
1387 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */ in dmfe_descriptor_init()
1400 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) { in dmfe_descriptor_init()
1401 tmp_rx->rdes0 = cpu_to_le32(0); in dmfe_descriptor_init()
1402 tmp_rx->rdes1 = cpu_to_le32(0x01000600); in dmfe_descriptor_init()
1424 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */ in update_cr6()
1440 void __iomem *ioaddr = db->ioaddr + 0xc0; in dm9132_id_table()
1446 for (i = 0; i < 3; i++) { in dm9132_id_table()
1447 dw16(0, addrptr[i]); in dm9132_id_table()
1452 memset(hash_table, 0, sizeof(hash_table)); in dm9132_id_table()
1455 hash_table[3] = 0x8000; in dm9132_id_table()
1459 u32 hash_val = cal_CRC((char *)ha->addr, 6, 0) & 0x3f; in dm9132_id_table()
1465 for (i = 0; i < 4; i++, ioaddr += 4) in dm9132_id_table()
1466 dw16(0, hash_table[i]); in dm9132_id_table()
1484 DMFE_DBUG(0, "send_filter_frame()", 0); in send_filter_frame()
1491 *suptr++ = addrptr[0]; in send_filter_frame()
1496 *suptr++ = 0xffff; in send_filter_frame()
1497 *suptr++ = 0xffff; in send_filter_frame()
1498 *suptr++ = 0xffff; in send_filter_frame()
1503 *suptr++ = addrptr[0]; in send_filter_frame()
1509 *suptr++ = 0xffff; in send_filter_frame()
1510 *suptr++ = 0xffff; in send_filter_frame()
1511 *suptr++ = 0xffff; in send_filter_frame()
1516 txptr->tdes1 = cpu_to_le32(0x890000c0); in send_filter_frame()
1524 txptr->tdes0 = cpu_to_le32(0x80000000); in send_filter_frame()
1525 update_cr6(db->cr6_data | 0x2000, ioaddr); in send_filter_frame()
1526 dw32(DCR1, 0x1); /* Issue Tx polling */ in send_filter_frame()
1554 rxptr->rdes0 = cpu_to_le32(0x80000000); in allocate_rx_buffer()
1571 for (i = 0; i < ARRAY_SIZE(cmd); i++) { in srom_clk_write()
1596 for (i = 5; i >= 0; i--) { in read_srom_word()
1604 for (i = 16; i > 0; i--) { in read_srom_word()
1608 ((dr32(DCR9) & CR9_CRDOUT) ? 1 : 0); in read_srom_word()
1626 u8 ErrFlag = 0; in dmfe_sense_speed()
1629 /* CR6 bit18=0, select 10/100M */ in dmfe_sense_speed()
1630 update_cr6(db->cr6_data & ~0x40000, ioaddr); in dmfe_sense_speed()
1635 if ( (phy_mode & 0x24) == 0x24 ) { in dmfe_sense_speed()
1638 db->phy_addr, 7, db->chip_id) & 0xf000; in dmfe_sense_speed()
1641 db->phy_addr, 17, db->chip_id) & 0xf000; in dmfe_sense_speed()
1643 case 0x1000: db->op_mode = DMFE_10MHF; break; in dmfe_sense_speed()
1644 case 0x2000: db->op_mode = DMFE_10MFD; break; in dmfe_sense_speed()
1645 case 0x4000: db->op_mode = DMFE_100MHF; break; in dmfe_sense_speed()
1646 case 0x8000: db->op_mode = DMFE_100MFD; break; in dmfe_sense_speed()
1653 DMFE_DBUG(0, "Link Failed :", phy_mode); in dmfe_sense_speed()
1673 db->cr6_data &= ~0x40000; in dmfe_set_phyxcer()
1676 /* DM9009 Chip: Phyxcer reg18 bit12=0 */ in dmfe_set_phyxcer()
1679 db->phy_addr, 18, db->chip_id) & ~0x1000; in dmfe_set_phyxcer()
1686 phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0; in dmfe_set_phyxcer()
1694 case DMFE_10MHF: phy_reg |= 0x20; break; in dmfe_set_phyxcer()
1695 case DMFE_10MFD: phy_reg |= 0x40; break; in dmfe_set_phyxcer()
1696 case DMFE_100MHF: phy_reg |= 0x80; break; in dmfe_set_phyxcer()
1697 case DMFE_100MFD: phy_reg |= 0x100; break; in dmfe_set_phyxcer()
1699 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61; in dmfe_set_phyxcer()
1703 if ( !(phy_reg & 0x01e0)) { in dmfe_set_phyxcer()
1711 dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id); in dmfe_set_phyxcer()
1713 dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id); in dmfe_set_phyxcer()
1729 if (db->op_mode & 0x4) in dmfe_process_mode()
1735 if (db->op_mode & 0x10) /* 1M HomePNA */ in dmfe_process_mode()
1736 db->cr6_data |= 0x40000;/* External MII select */ in dmfe_process_mode()
1738 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */ in dmfe_process_mode()
1743 if ( !(db->media_mode & 0x18)) { in dmfe_process_mode()
1746 if ( !(phy_reg & 0x1) ) { in dmfe_process_mode()
1748 phy_reg = 0x0; in dmfe_process_mode()
1750 case DMFE_10MHF: phy_reg = 0x0; break; in dmfe_process_mode()
1751 case DMFE_10MFD: phy_reg = 0x100; break; in dmfe_process_mode()
1752 case DMFE_100MHF: phy_reg = 0x2000; break; in dmfe_process_mode()
1753 case DMFE_100MFD: phy_reg = 0x2100; break; in dmfe_process_mode()
1756 db->phy_addr, 0, phy_reg, db->chip_id); in dmfe_process_mode()
1760 db->phy_addr, 0, phy_reg, db->chip_id); in dmfe_process_mode()
1776 dw16(0x80 + offset * 4, phy_data); in dmfe_phy_write()
1781 for (i = 0; i < 35; i++) in dmfe_phy_write()
1793 for (i = 0x10; i > 0; i = i >> 1) in dmfe_phy_write()
1798 for (i = 0x10; i > 0; i = i >> 1) in dmfe_phy_write()
1807 for ( i = 0x8000; i > 0; i >>= 1) in dmfe_phy_write()
1825 phy_data = dr16(0x80 + offset * 4); in dmfe_phy_read()
1830 for (i = 0; i < 35; i++) in dmfe_phy_read()
1842 for (i = 0x10; i > 0; i = i >> 1) in dmfe_phy_read()
1847 for (i = 0x10; i > 0; i = i >> 1) in dmfe_phy_read()
1855 for (phy_data = 0, i = 0; i < 16; i++) { in dmfe_phy_read()
1888 dw32(DCR9, 0x50000); in dmfe_phy_read_1bit()
1890 phy_data = (dr32(DCR9) >> 19) & 0x1; in dmfe_phy_read_1bit()
1891 dw32(DCR9, 0x40000); in dmfe_phy_read_1bit()
1907 DMFE_DBUG(0, "dmfe_parse_srom() ", 0); in dmfe_parse_srom()
1913 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) { in dmfe_parse_srom()
1917 db->PHY_reg4 = 0; in dmfe_parse_srom()
1918 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) { in dmfe_parse_srom()
1920 case 0x1: db->PHY_reg4 |= 0x0020; break; in dmfe_parse_srom()
1921 case 0x2: db->PHY_reg4 |= 0x0040; break; in dmfe_parse_srom()
1922 case 0x4: db->PHY_reg4 |= 0x0080; break; in dmfe_parse_srom()
1923 case 0x8: db->PHY_reg4 |= 0x0100; break; in dmfe_parse_srom()
1931 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */ in dmfe_parse_srom()
1932 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */ in dmfe_parse_srom()
1933 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */ in dmfe_parse_srom()
1934 case 0x100: in dmfe_parse_srom()
1935 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */ in dmfe_parse_srom()
1940 if ( (SF_mode & 0x1) || (srom[43] & 0x80) ) in dmfe_parse_srom()
1941 db->cr15_data |= 0x40; in dmfe_parse_srom()
1944 if ( (SF_mode & 0x2) || (srom[40] & 0x1) ) in dmfe_parse_srom()
1945 db->cr15_data |= 0x400; in dmfe_parse_srom()
1948 if ( (SF_mode & 0x4) || (srom[40] & 0xe) ) in dmfe_parse_srom()
1949 db->cr15_data |= 0x9800; in dmfe_parse_srom()
1956 if (HPNA_rx_cmd == 0) in dmfe_parse_srom()
1957 db->HPNA_command |= 0x8000; in dmfe_parse_srom()
1962 case 0: db->HPNA_command |= 0x0904; break; in dmfe_parse_srom()
1963 case 1: db->HPNA_command |= 0x0a00; break; in dmfe_parse_srom()
1964 case 2: db->HPNA_command |= 0x0506; break; in dmfe_parse_srom()
1965 case 3: db->HPNA_command |= 0x0602; break; in dmfe_parse_srom()
1969 case 0: db->HPNA_command |= 0x0004; break; in dmfe_parse_srom()
1970 case 1: db->HPNA_command |= 0x0000; break; in dmfe_parse_srom()
1971 case 2: db->HPNA_command |= 0x0006; break; in dmfe_parse_srom()
1972 case 3: db->HPNA_command |= 0x0002; break; in dmfe_parse_srom()
1976 db->HPNA_present = 0; in dmfe_parse_srom()
1977 update_cr6(db->cr6_data | 0x40000, db->ioaddr); in dmfe_parse_srom()
1979 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) { in dmfe_parse_srom()
1982 if ( dmfe_phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) { in dmfe_parse_srom()
2006 case 0xb900: /* DM9801 E3 */ in dmfe_program_DM9801()
2007 db->HPNA_command |= 0x1000; in dmfe_program_DM9801()
2009 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000; in dmfe_program_DM9801()
2012 case 0xb901: /* DM9801 E4 */ in dmfe_program_DM9801()
2014 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor; in dmfe_program_DM9801()
2016 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3; in dmfe_program_DM9801()
2018 case 0xb902: /* DM9801 E5 */ in dmfe_program_DM9801()
2019 case 0xb903: /* DM9801 E6 */ in dmfe_program_DM9801()
2021 db->HPNA_command |= 0x1000; in dmfe_program_DM9801()
2023 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5; in dmfe_program_DM9801()
2025 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor; in dmfe_program_DM9801()
2045 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor; in dmfe_program_DM9802()
2060 phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60; in dmfe_HPNA_remote_cmd_chk()
2062 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */ in dmfe_HPNA_remote_cmd_chk()
2063 case 0x20: phy_reg = 0x0900;break; /* LP/HS */ in dmfe_HPNA_remote_cmd_chk()
2064 case 0x40: phy_reg = 0x0600;break; /* HP/LS */ in dmfe_HPNA_remote_cmd_chk()
2065 case 0x60: phy_reg = 0x0500;break; /* HP/HS */ in dmfe_HPNA_remote_cmd_chk()
2069 if ( phy_reg != (db->HPNA_command & 0x0f00) ) { in dmfe_HPNA_remote_cmd_chk()
2080 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2081 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2082 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2083 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2084 { 0, }
2102 dw32(DCR7, 0); in dmfe_suspend()
2111 return 0; in dmfe_suspend()
2127 return 0; in dmfe_resume()
2144 module_param(debug, int, 0);
2145 module_param(mode, byte, 0);
2146 module_param(cr6set, int, 0);
2147 module_param(chkmode, byte, 0);
2148 module_param(HPNA_mode, byte, 0);
2149 module_param(HPNA_rx_cmd, byte, 0);
2150 module_param(HPNA_tx_cmd, byte, 0);
2151 module_param(HPNA_NoiseFloor, byte, 0);
2152 module_param(SF_mode, byte, 0);
2153 MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
2155 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2158 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
2169 DMFE_DBUG(0, "init_module() ", debug); in dmfe_init_module()
2190 HPNA_mode = 0; /* Default: LP/HS */ in dmfe_init_module()
2192 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */ in dmfe_init_module()
2194 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */ in dmfe_init_module()
2196 HPNA_NoiseFloor = 0; in dmfe_init_module()
2199 if (rc < 0) in dmfe_init_module()
2202 return 0; in dmfe_init_module()
2214 DMFE_DBUG(0, "dmfe_cleanup_module() ", debug); in dmfe_cleanup_module()