Home
last modified time | relevance | path

Searched +full:0 +full:x80010000 (Results 1 – 25 of 36) sorted by relevance

12

/Linux-v5.15/drivers/firmware/efi/
Dsysfb_efi.c32 OVERRIDE_NONE = 0x0,
33 OVERRIDE_BASE = 0x1,
34 OVERRIDE_STRIDE = 0x2,
35 OVERRIDE_HEIGHT = 0x4,
36 OVERRIDE_WIDTH = 0x8,
40 [M_I17] = { "i17", 0x80010000, 1472 * 4, 1440, 900, OVERRIDE_NONE },
41 [M_I20] = { "i20", 0x80010000, 1728 * 4, 1680, 1050, OVERRIDE_NONE }, /* guess */
42 [M_I20_SR] = { "imac7", 0x40010000, 1728 * 4, 1680, 1050, OVERRIDE_NONE },
43 [M_I24] = { "i24", 0x80010000, 2048 * 4, 1920, 1200, OVERRIDE_NONE }, /* guess */
44 [M_I24_8_1] = { "imac8", 0xc0060000, 2048 * 4, 1920, 1200, OVERRIDE_NONE },
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/sound/
Dxlnx,spdif.txt13 - xlnx,spdif-mode: 0 :- receiver mode
24 interrupts = <0 91 4>;
25 reg = <0x0 0x80010000 0x0 0x10000>;
Dxlnx,audio-formatter.txt25 interrupts = <0 104 4>, <0 105 4>;
26 reg = <0x0 0x80010000 0x0 0x1000>;
28 clocks = <&clk 71>, <&clk_wiz_1 0>;
/Linux-v5.15/Documentation/devicetree/bindings/spi/
Dmxs-spi.yaml50 #size-cells = <0>;
52 reg = <0x80010000 0x2000>;
54 dmas = <&dma_apbh 0>;
Dspi-controller.yaml20 pattern: "^spi(@.*|-[0-9a-f])*$"
23 enum: [0, 1]
26 const: 0
36 cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
40 cs0 : &gpio1 0 0
42 cs2 : &gpio1 1 0
43 cs3 : &gpio1 2 0
45 The second flag of a gpio descriptor can be GPIO_ACTIVE_HIGH (0)
46 or GPIO_ACTIVE_LOW(1). Legacy device trees often use 0.
94 "^.*@[0-9a-f]+$":
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/mmc/
Dmxs-mmc.yaml53 reg = <0x80010000 2000>;
55 dmas = <&dma_apbh 0>;
/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dalphascale,acc.txt22 CLKID_AHB_ROM 0
102 reg = <0x80010000 0x4000>;
110 reg = <0x80088000 0x4000>;
/Linux-v5.15/arch/arm/boot/dts/
Dspear300.dtsi15 ranges = <0x60000000 0x60000000 0x50000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0x99000000 0x1000>;
25 reg = <0x60000000 0x1000>;
34 reg = <0x94000000 0x1000 /* FSMC Register */
35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
37 0x80010000 0x0010>; /* NAND Base CMD */
44 reg = <0x70000000 0x100>;
49 shirq: interrupt-controller@0x50000000 {
[all …]
Dimx23.dtsi32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
45 reg = <0x80000000 0x80000>;
52 reg = <0x80000000 0x40000>;
59 reg = <0x80000000 0x2000>;
64 reg = <0x80004000 0x2000>;
65 interrupts = <0 14 20 0
75 reg = <0x80008000 0x2000>;
83 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
[all …]
/Linux-v5.15/arch/arm/mach-sa1100/
Dh3xxx.c35 .size = 0x00040000,
36 .offset = 0,
41 .offset = 0x00040000,
58 err = gpio_direction_output(H3XXX_EGPIO_VPP_ON, 0); in h3xxx_flash_init()
112 err = 0; in h3xxx_uart_set_wake()
137 [0] = DEFINE_RES_MEM(H3600_EGPIO_PHYS, 0x4),
141 [0] = {
142 .reg_start = 0,
146 .initial_values = 0x0080, /* H3XXX_EGPIO_RS232_ON */
185 .wakeup = 0,
[all …]
/Linux-v5.15/include/uapi/video/
Dsisfb.h33 #define CRT2_DEFAULT 0x00000001
34 #define CRT2_LCD 0x00000002
35 #define CRT2_TV 0x00000004
36 #define CRT2_VGA 0x00000008
37 #define TV_NTSC 0x00000010
38 #define TV_PAL 0x00000020
39 #define TV_HIVISION 0x00000040
40 #define TV_YPBPR 0x00000080
41 #define TV_AVIDEO 0x00000100
42 #define TV_SVIDEO 0x00000200
[all …]
/Linux-v5.15/arch/mips/netlogic/common/
Dreset.S54 XLP_IO_SYS_OFFSET(0) + XLP_IO_PCI_HDRSZ + \
62 lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */
68 ori t1, 0x1000 /* Enable Icache partitioning */
72 lui t1, 0x0100 /* Disable BRU accepting ALU ops */
96 slt t1, t0, 0x1200
103 li t2, 0 /* index */
104 li t3, 0x1000 /* loop count */
108 ori v1, v0, 0x3 /* way0 | write_enable | write_active */
112 andi v1, 0x1 /* wait for write_active == 0 */
116 ori v1, v0, 0x7 /* way1 | write_enable | write_active */
[all …]
/Linux-v5.15/arch/mips/kernel/
Dbmips_vec.S35 * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is
37 * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.
54 /* set up CPU1 CBR; move BASE to 0xa000_0000 */
55 li k0, 0xff400000
60 andi k1, 0x8000
63 li k1, 0xa0080000
64 sw k1, 0(k0)
78 * entire function gets copied to 0x8000_0000.
100 /* if we're not on core 0, this must be the SMP boot signal */
134 andi k0, 0xff00
[all …]
/Linux-v5.15/sound/soc/mediatek/mt8183/
Dmt8183-dai-adda.c15 AUDIO_SDM_LEVEL_MUTE = 0,
16 AUDIO_SDM_LEVEL_NORMAL = 0x1d,
22 DELAY_DATA_MISO1 = 0,
27 MTK_AFE_ADDA_DL_RATE_8K = 0,
41 MTK_AFE_ADDA_UL_RATE_8K = 0,
108 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
109 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
110 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
112 I_ADDA_UL_CH2, 1, 0),
114 I_ADDA_UL_CH1, 1, 0),
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/
Dredwood.dts18 dcr-parent = <&{/cpus/cpu@0}>;
27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
[all …]
Dicon.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
[all …]
Dkatmai.dts22 dcr-parent = <&{/cpus/cpu@0}>;
33 #size-cells = <0>;
35 cpu@0 {
38 reg = <0x00000000>;
39 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */
53 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
59 cell-index = <0>;
60 dcr-reg = <0x0c0 0x009>;
61 #address-cells = <0>;
[all …]
Dcanyonlands.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
[all …]
/Linux-v5.15/include/asm-generic/
Dhyperv-tlfs.h50 #define HV_MSR_VP_RUNTIME_AVAILABLE BIT(0)
81 #define HV_CREATE_PARTITIONS BIT(0)
121 * 62:56 - Os Type; Linux is 0x100
124 * 15:0 - Distro specific identification
129 #define HV_LINUX_VENDOR_ID 0x8100
138 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002
139 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003
140 #define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008
141 #define HVCALL_SEND_IPI 0x000b
142 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Djpeg_v1_0.c41 …ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACK… in jpeg_v1_0_decode_ring_patch_wreg()
42 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_patch_wreg()
43 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_patch_wreg()
44 ring->ring[(*ptr)++] = 0; in jpeg_v1_0_decode_ring_patch_wreg()
45 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0); in jpeg_v1_0_decode_ring_patch_wreg()
48 ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0); in jpeg_v1_0_decode_ring_patch_wreg()
60 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW); in jpeg_v1_0_decode_ring_set_patch_ring()
66 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH); in jpeg_v1_0_decode_ring_set_patch_ring()
72 for (i = 0; i <= 2; i++) { in jpeg_v1_0_decode_ring_set_patch_ring()
73 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2); in jpeg_v1_0_decode_ring_set_patch_ring()
[all …]
Djpeg_v2_0.c35 #define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff
36 #define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x4029
37 #define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x402a
38 #define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x402b
39 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ea
40 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40eb
41 #define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40cf
42 #define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40d1
43 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40e8
44 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40e9
[all …]
/Linux-v5.15/include/rdma/
Dib_mad.h20 #define OPA_MGMT_BASE_VERSION 0x80
22 #define OPA_SM_CLASS_VERSION 0x80
25 #define IB_MGMT_CLASS_SUBN_LID_ROUTED 0x01
26 #define IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE 0x81
27 #define IB_MGMT_CLASS_SUBN_ADM 0x03
28 #define IB_MGMT_CLASS_PERF_MGMT 0x04
29 #define IB_MGMT_CLASS_BM 0x05
30 #define IB_MGMT_CLASS_DEVICE_MGMT 0x06
31 #define IB_MGMT_CLASS_CM 0x07
32 #define IB_MGMT_CLASS_SNMP 0x08
[all …]
/Linux-v5.15/arch/m68k/fpsp040/
Dsetox.S80 | 2.1 Set AdjFlag := 0 (indicates the branch 1.3 -> 2 was taken)
82 | 2.3 Calculate J = N mod 64; so J = 0,1,2,..., or 63.
154 | 6.1 If AdjFlag = 0, go to 6.3
158 | Notes: If AdjFlag = 0, we have X = Mlog2 + Jlog2/64 + R,
189 | 8.3 Calculate J = N mod 64, J = 0,1,...,63
197 | 9.1 If X < 0, go to 9.3
212 | Step 1. Set ans := 0
234 | 2.2 Calculate J = N mod 64; so J = 0,1,2,..., or 63.
343 L2: .long 0x3FDC0000,0x82E30865,0x4361C4C6,0x00000000
345 EXPA3: .long 0x3FA55555,0x55554431
[all …]
Dsatan.S55 BOUNDS1: .long 0x3FFB8000,0x4002FFFF
57 ONE: .long 0x3F800000
59 .long 0x00000000
61 ATANA3: .long 0xBFF6687E,0x314987D8
62 ATANA2: .long 0x4002AC69,0x34A26DB3
64 ATANA1: .long 0xBFC2476F,0x4E1DA28E
65 ATANB6: .long 0x3FB34444,0x7F876989
67 ATANB5: .long 0xBFB744EE,0x7FAF45DB
68 ATANB4: .long 0x3FBC71C6,0x46940220
70 ATANB3: .long 0xBFC24924,0x921872F9
[all …]
/Linux-v5.15/arch/arm/
DKconfig.debug140 0x80000000 | 0xf0000000 | UART0
141 0x80004000 | 0xf0004000 | UART1
142 0x80008000 | 0xf0008000 | UART2
143 0x8000c000 | 0xf000c000 | UART3
144 0x80010000 | 0xf0010000 | UART4
145 0x80014000 | 0xf0014000 | UART5
146 0x80018000 | 0xf0018000 | UART6
147 0x8001c000 | 0xf001c000 | UART7
148 0x80020000 | 0xf0020000 | UART8
149 0x80024000 | 0xf0024000 | UART9
[all …]

12