Lines Matching +full:0 +full:x80010000
54 XLP_IO_SYS_OFFSET(0) + XLP_IO_PCI_HDRSZ + \
62 lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */
68 ori t1, 0x1000 /* Enable Icache partitioning */
72 lui t1, 0x0100 /* Disable BRU accepting ALU ops */
96 slt t1, t0, 0x1200
103 li t2, 0 /* index */
104 li t3, 0x1000 /* loop count */
108 ori v1, v0, 0x3 /* way0 | write_enable | write_active */
112 andi v1, 0x1 /* wait for write_active == 0 */
116 ori v1, v0, 0x7 /* way1 | write_enable | write_active */
120 andi v1, 0x1 /* wait for write_active == 0 */
131 li t0, 0x80000000
132 li t1, 0x80010000
133 16: cache Index_Writeback_Inv_D, 0(t0)
163 li k1, 0x80000
175 li t1, 0x1500 /* XLP 9xx */
179 li t1, 0x1300 /* XLP 5xx */
187 andi t1, 0x3 /* t1 <- node */
188 li t2, 0x40000
189 mul t3, t2, t1 /* t3 = node * 0x40000 */
191 and t0, t0, 0x7 /* t0 <- core */
192 li t1, 0x1
197 lw t1, 0(t2)
199 sw t1, 0(t2)
202 lw t1, 0(t2)
206 /* Configure LSU on Non-0 Cores. */
229 * For all the cases other than core 0 thread 0, we will
235 andi v0, 0x3ff /* v0 <- node/core */
241 andi v1, v0, 0x3 /* v1 <- thread id */
245 /* thread 0 of each core. */
248 subu t1, 0x3 /* 4-thread per core mode? */
253 li t1, 0x55
257 beqz v0, 4f /* boot cpu (cpuid == 0)? */
275 sw t2, 0(t1)