Lines Matching +full:0 +full:x80010000
35 #define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff
36 #define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x4029
37 #define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x402a
38 #define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x402b
39 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ea
40 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40eb
41 #define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40cf
42 #define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40d1
43 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40e8
44 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40e9
45 #define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET 0x4082
46 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ec
47 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ed
48 #define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET 0x4085
49 #define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET 0x4084
50 #define mmUVD_JRBC_STATUS_INTERNAL_OFFSET 0x4089
51 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
53 #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000
76 return 0; in jpeg_v2_0_early_init()
111 0, AMDGPU_RING_PRIO_DEFAULT, NULL); in jpeg_v2_0_sw_init()
116 adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); in jpeg_v2_0_sw_init()
118 return 0; in jpeg_v2_0_sw_init()
155 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); in jpeg_v2_0_hw_init()
178 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS)) in jpeg_v2_0_hw_fini()
181 return 0; in jpeg_v2_0_hw_fini()
229 int r = 0; in jpeg_v2_0_disable_power_gating()
233 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); in jpeg_v2_0_disable_power_gating()
235 r = SOC15_WAIT_ON_RREG(JPEG, 0, in jpeg_v2_0_disable_power_gating()
246 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1; in jpeg_v2_0_disable_power_gating()
247 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data); in jpeg_v2_0_disable_power_gating()
249 return 0; in jpeg_v2_0_disable_power_gating()
256 int r = 0; in jpeg_v2_0_enable_power_gating()
258 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)); in jpeg_v2_0_enable_power_gating()
260 data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF; in jpeg_v2_0_enable_power_gating()
261 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data); in jpeg_v2_0_enable_power_gating()
264 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); in jpeg_v2_0_enable_power_gating()
266 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, in jpeg_v2_0_enable_power_gating()
276 return 0; in jpeg_v2_0_enable_power_gating()
283 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); in jpeg_v2_0_disable_clock_gating()
291 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); in jpeg_v2_0_disable_clock_gating()
293 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v2_0_disable_clock_gating()
299 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); in jpeg_v2_0_disable_clock_gating()
306 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); in jpeg_v2_0_enable_clock_gating()
310 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in jpeg_v2_0_enable_clock_gating()
314 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); in jpeg_v2_0_enable_clock_gating()
316 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v2_0_enable_clock_gating()
322 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); in jpeg_v2_0_enable_clock_gating()
348 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in jpeg_v2_0_start()
351 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0, in jpeg_v2_0_start()
355 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN), in jpeg_v2_0_start()
359 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v2_0_start()
360 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v2_0_start()
361 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, in jpeg_v2_0_start()
363 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, in jpeg_v2_0_start()
365 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); in jpeg_v2_0_start()
366 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); in jpeg_v2_0_start()
367 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); in jpeg_v2_0_start()
368 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v2_0_start()
369 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v2_0_start()
371 return 0; in jpeg_v2_0_start()
386 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), in jpeg_v2_0_stop()
401 return 0; in jpeg_v2_0_stop()
415 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v2_0_dec_ring_get_rptr()
432 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v2_0_dec_ring_get_wptr()
450 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v2_0_dec_ring_set_wptr()
464 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_insert_start()
465 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_start()
468 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_insert_start()
469 amdgpu_ring_write(ring, 0x80010000); in jpeg_v2_0_dec_ring_insert_start()
482 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_insert_end()
483 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_end()
486 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_insert_end()
487 amdgpu_ring_write(ring, 0x00010000); in jpeg_v2_0_dec_ring_insert_end()
506 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_fence()
510 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_fence()
514 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_fence()
518 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_fence()
522 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_fence()
523 amdgpu_ring_write(ring, 0x8); in jpeg_v2_0_dec_ring_emit_fence()
526 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); in jpeg_v2_0_dec_ring_emit_fence()
527 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_fence()
530 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_fence()
531 amdgpu_ring_write(ring, 0x3fbc); in jpeg_v2_0_dec_ring_emit_fence()
534 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_fence()
535 amdgpu_ring_write(ring, 0x1); in jpeg_v2_0_dec_ring_emit_fence()
537 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); in jpeg_v2_0_dec_ring_emit_fence()
538 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_fence()
559 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
563 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
567 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
571 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
575 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
579 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
583 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
586 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); in jpeg_v2_0_dec_ring_emit_ib()
587 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_ib()
590 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
591 amdgpu_ring_write(ring, 0x01400200); in jpeg_v2_0_dec_ring_emit_ib()
594 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
595 amdgpu_ring_write(ring, 0x2); in jpeg_v2_0_dec_ring_emit_ib()
598 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); in jpeg_v2_0_dec_ring_emit_ib()
599 amdgpu_ring_write(ring, 0x2); in jpeg_v2_0_dec_ring_emit_ib()
608 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_reg_wait()
609 amdgpu_ring_write(ring, 0x01400200); in jpeg_v2_0_dec_ring_emit_reg_wait()
612 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_reg_wait()
616 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_reg_wait()
617 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { in jpeg_v2_0_dec_ring_emit_reg_wait()
618 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_reg_wait()
620 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); in jpeg_v2_0_dec_ring_emit_reg_wait()
624 0, 0, PACKETJ_TYPE3)); in jpeg_v2_0_dec_ring_emit_reg_wait()
640 mask = 0xffffffff; in jpeg_v2_0_dec_ring_emit_vm_flush()
649 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_wreg()
650 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { in jpeg_v2_0_dec_ring_emit_wreg()
651 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_wreg()
653 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_wreg()
657 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_wreg()
668 for (i = 0; i < count / 2; i++) { in jpeg_v2_0_dec_ring_nop()
669 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); in jpeg_v2_0_dec_ring_nop()
670 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_nop()
678 return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) & in jpeg_v2_0_is_idle()
688 ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK, in jpeg_v2_0_wait_for_idle()
708 return 0; in jpeg_v2_0_set_clockgating_state()
718 return 0; in jpeg_v2_0_set_powergating_state()
736 return 0; in jpeg_v2_0_set_interrupt_state()
751 entry->src_id, entry->src_data[0]); in jpeg_v2_0_process_interrupt()
755 return 0; in jpeg_v2_0_process_interrupt()
780 .align_mask = 0xf,
829 .minor = 0,
830 .rev = 0,