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/Linux-v6.1/drivers/bus/
Domap_l3_smx.h14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
/Linux-v6.1/drivers/dma/ti/
Dk3-psil-priv.h25 * 0x4400 and 0xc400) only the src configuration can be present. If no dst
26 * configuration found the code will look for (dst_thread_id & ~0x8000) to find
Dk3-psil-am654.c54 PSIL_SA2UL(0x4000, 0),
55 PSIL_SA2UL(0x4001, 0),
56 PSIL_SA2UL(0x4002, 0),
57 PSIL_SA2UL(0x4003, 0),
59 PSIL_ETHERNET(0x4100),
60 PSIL_ETHERNET(0x4101),
61 PSIL_ETHERNET(0x4102),
62 PSIL_ETHERNET(0x4103),
64 PSIL_ETHERNET(0x4200),
65 PSIL_ETHERNET(0x4201),
[all …]
Dk3-psil-j721s2.c63 PSIL_PDMA_MCASP(0x4400),
64 PSIL_PDMA_MCASP(0x4401),
65 PSIL_PDMA_MCASP(0x4402),
66 PSIL_PDMA_MCASP(0x4403),
67 PSIL_PDMA_MCASP(0x4404),
69 PSIL_PDMA_XY_PKT(0x4600),
70 PSIL_PDMA_XY_PKT(0x4601),
71 PSIL_PDMA_XY_PKT(0x4602),
72 PSIL_PDMA_XY_PKT(0x4603),
73 PSIL_PDMA_XY_PKT(0x4604),
[all …]
Dk3-psil-am62.c73 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
74 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
75 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
76 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
78 PSIL_PDMA_XY_PKT(0x4302),
79 PSIL_PDMA_XY_PKT(0x4303),
80 PSIL_PDMA_XY_PKT(0x4304),
81 PSIL_PDMA_XY_PKT(0x4305),
82 PSIL_PDMA_XY_PKT(0x4306),
83 PSIL_PDMA_XY_PKT(0x4307),
[all …]
Dk3-psil-am64.c66 PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
67 PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
68 PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
69 PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
71 PSIL_ETHERNET(0x4100, 21, 48, 16),
72 PSIL_ETHERNET(0x4101, 22, 64, 16),
73 PSIL_ETHERNET(0x4102, 23, 80, 16),
74 PSIL_ETHERNET(0x4103, 24, 96, 16),
76 PSIL_ETHERNET(0x4200, 25, 112, 16),
77 PSIL_ETHERNET(0x4201, 26, 128, 16),
[all …]
Dk3-psil-j7200.c64 PSIL_PDMA_MCASP(0x4400),
65 PSIL_PDMA_MCASP(0x4401),
66 PSIL_PDMA_MCASP(0x4402),
68 PSIL_PDMA_XY_PKT(0x4600),
69 PSIL_PDMA_XY_PKT(0x4601),
70 PSIL_PDMA_XY_PKT(0x4602),
71 PSIL_PDMA_XY_PKT(0x4603),
72 PSIL_PDMA_XY_PKT(0x4604),
73 PSIL_PDMA_XY_PKT(0x4605),
74 PSIL_PDMA_XY_PKT(0x4606),
[all …]
Dk3-psil-j721e.c72 PSIL_SA2UL(0x4000, 0),
73 PSIL_SA2UL(0x4001, 0),
74 PSIL_SA2UL(0x4002, 0),
75 PSIL_SA2UL(0x4003, 0),
77 PSIL_ETHERNET(0x4100),
78 PSIL_ETHERNET(0x4101),
79 PSIL_ETHERNET(0x4102),
80 PSIL_ETHERNET(0x4103),
82 PSIL_ETHERNET(0x4200),
83 PSIL_ETHERNET(0x4201),
[all …]
/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dnv10.c34 u32 pipe_0x0000[0x040/4];
35 u32 pipe_0x0040[0x010/4];
36 u32 pipe_0x0200[0x0c0/4];
37 u32 pipe_0x4400[0x080/4];
38 u32 pipe_0x6400[0x3b0/4];
39 u32 pipe_0x6800[0x2f0/4];
40 u32 pipe_0x6c00[0x030/4];
41 u32 pipe_0x7000[0x130/4];
42 u32 pipe_0x7400[0x0c0/4];
43 u32 pipe_0x7800[0x0c0/4];
[all …]
/Linux-v6.1/drivers/regulator/
Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
/Linux-v6.1/arch/arm64/boot/dts/ti/
Dk3-am65-mcu.dtsi11 reg = <0x0 0x40f00000 0x0 0x20000>;
14 ranges = <0x0 0x0 0x40f00000 0x20000>;
18 reg = <0x4040 0x4>;
25 reg = <0x00 0x40a00000 0x00 0x100>;
34 reg = <0x00 0x41c00000 0x00 0x80000>;
35 ranges = <0x0 0x00 0x41c00000 0x80000>;
42 reg = <0x0 0x40b00000 0x0 0x100>;
45 #size-cells = <0>;
53 reg = <0x0 0x40300000 0x0 0x400>;
58 #size-cells = <0>;
[all …]
/Linux-v6.1/lib/
Dcrc16.c10 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
12 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
13 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
14 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
15 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
16 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
17 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
18 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
19 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
20 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/sound/
Ddavinci-mcasp-audio.yaml35 description: 0 - I2S or 1 - DIT operation mode
37 - 0
52 0 - Inactive, 1 - TX, 2 - RX
58 minimum: 0
83 0 disables the FIFO use
90 0 disables the FIFO use
97 0 - 3-state, 2 - logic low, 3 - logic high
99 - 0
154 const: 0
174 - 0
[all …]
/Linux-v6.1/drivers/gpu/drm/sun4i/
Dsun4i_backend.h20 #define SUN4I_BACKEND_MODCTL_REG 0x800
24 #define SUN4I_BACKEND_MODCTL_OUT_LCD0 (0 << 20)
34 #define SUN4I_BACKEND_MODCTL_DEBE_EN BIT(0)
36 #define SUN4I_BACKEND_BACKCOLOR_REG 0x804
39 #define SUN4I_BACKEND_DISSIZE_REG 0x808
40 #define SUN4I_BACKEND_DISSIZE(w, h) (((((h) - 1) & 0xffff) << 16) | \
41 (((w) - 1) & 0xffff))
43 #define SUN4I_BACKEND_LAYSIZE_REG(l) (0x810 + (0x4 * (l)))
44 #define SUN4I_BACKEND_LAYSIZE(w, h) (((((h) - 1) & 0x1fff) << 16) | \
45 (((w) - 1) & 0x1fff))
[all …]
/Linux-v6.1/drivers/gpu/drm/msm/adreno/
Da4xx_gpu.c30 for (i = 0; i < submit->nr_cmds; i++) { in a4xx_submit()
61 OUT_RING(ring, 0x00000000); in a4xx_submit()
80 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
81 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
82 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
83 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
84 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
85 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
86 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
87 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
[all …]
/Linux-v6.1/drivers/gpu/drm/i915/display/
Dintel_dsi_vbt.c51 #define MIPI_TRANSFER_MODE_SHIFT 0
56 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
57 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
58 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
59 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
60 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
61 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
62 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
63 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
64 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dsama7g5.dtsi28 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0>;
78 #clock-cells = <0>;
83 #clock-cells = <0>;
88 #clock-cells = <0>;
107 reg = <0x100000 0x20000>;
120 reg = <0x00600000 0x2400>;
123 ranges = <0 0x00600000 0x2400>;
128 reg = <0x10000000 0x8000000>;
[all …]
/Linux-v6.1/arch/mips/include/asm/
Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/Linux-v6.1/drivers/misc/habanalabs/include/gaudi2/asic_reg/
Dgaudi2_blocks_linux_driver.h16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
[all …]
/Linux-v6.1/drivers/net/ethernet/amd/
Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/Linux-v6.1/arch/m68k/fpsp040/
Dbugfix.S21 | dirty_bit[cmdreg3b[9:7]] = 0;
181 andib #0xFE,%d0
191 | Check for opclass 0. If not, go and check for opclass 2 and sgl.
194 andiw #0xE000,%d0 |strip all but opclass
195 bne op2sgl |not opclass 0, check op2
222 | We have the opclass 0 situation.
232 moveb #0x12,%d0
233 bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, extended
269 andil #0xe0000000,L_SCR3(%a6)
270 moveb #0,CU_SAVEPC(%a6)
[all …]
/Linux-v6.1/drivers/pinctrl/mediatek/
Dpinctrl-mt7629.c12 MTK_PIN(_number, _name, 0, _eint_n, DRV_GRP1)
15 PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
19 PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
23 PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
27 PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
31 PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
32 PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
33 PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
34 PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
35 PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/fpga/
Dfpga-region.txt210 bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by
218 reg = <0xff706000 0x1000
219 0xffb90000 0x20>;
220 interrupts = <0 175 4>;
225 reg = <0xff400000 0x100000>;
241 reg = <0xff500000 0x10000>;
257 ranges = <0x20000 0xff200000 0x100000>,
258 <0x0 0xc0000000 0x20000000>;
262 reg = <0x10040 0x20>;
272 reg = <0x0 0x10000>;
[all …]
/Linux-v6.1/sound/isa/sb/
Demu8000.c99 unsigned right_bit = (mode & EMU8000_RAM_RIGHT) ? 0x01000000 : 0; in snd_emu8000_dma_chan()
102 EMU8000_CCCA_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
103 EMU8000_DCYSUSV_WRITE(emu, ch, 0x807F); in snd_emu8000_dma_chan()
106 EMU8000_DCYSUSV_WRITE(emu, ch, 0x80); in snd_emu8000_dma_chan()
107 EMU8000_VTFT_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
108 EMU8000_CVCF_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
109 EMU8000_PTRX_WRITE(emu, ch, 0x40000000); in snd_emu8000_dma_chan()
110 EMU8000_CPF_WRITE(emu, ch, 0x40000000); in snd_emu8000_dma_chan()
111 EMU8000_PSST_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
112 EMU8000_CSL_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
[all …]
/Linux-v6.1/drivers/gpu/drm/radeon/
Dr300.c93 for (i = 0; i < 2; i++) { in rv370_pcie_gart_tlb_flush()
102 #define R300_PTE_UNSNOOPED (1 << 0)
109 ((upper_32_bits(addr) & 0xff) << 24); in rv370_pcie_gart_get_page_entry()
136 return 0; in rv370_pcie_gart_init()
170 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_enable()
171 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); in rv370_pcie_gart_enable()
176 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); in rv370_pcie_gart_enable()
178 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); in rv370_pcie_gart_enable()
184 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", in rv370_pcie_gart_enable()
188 return 0; in rv370_pcie_gart_enable()
[all …]

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