51 #define MIPI_TRANSFER_MODE_SHIFT	0
56 #define VLV_GPIO_NC_0_HV_DDI0_HPD	0x4130
57 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA	0x4120
58 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL	0x4110
59 #define VLV_GPIO_NC_3_PANEL0_VDDEN	0x4140
60 #define VLV_GPIO_NC_4_PANEL0_BKLTEN	0x4150
61 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL	0x4160
62 #define VLV_GPIO_NC_6_HV_DDI1_HPD	0x4180
63 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA	0x4190
64 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL	0x4170
65 #define VLV_GPIO_NC_9_PANEL1_VDDEN	0x4100
66 #define VLV_GPIO_NC_10_PANEL1_BKLTEN	0x40E0
67 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL	0x40F0
98 #define CHV_GPIO_IDX_START_N		0
105 #define CHV_GPIO_PAD_CFG0(f, i)		(0x4400 + (f) * 0x400 + (i) * 8)
107 #define  CHV_GPIO_GPIOCFG_GPIO		(0 << 8)
113 #define CHV_GPIO_PAD_CFG1(f, i)		(0x4400 + (f) * 0x400 + (i) * 8 + 4)
117 #define  ICL_GPIO_DDSP_HPD_A		0
133 	 * send packet apparently always has 0 for the port. Just use the port  in intel_dsi_seq_port_to_port()
189 		mipi_dsi_generic_write(dsi_device, NULL, 0);  in mipi_exec_send_packet()
264 		if (gpio_source == 0) {  in vlv_exec_gpio()
282 		vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);  in vlv_exec_gpio()
286 	tmp = 0x4 | value;  in vlv_exec_gpio()
315 		if (gpio_source != 0) {  in chv_exec_gpio()
338 	vlv_iosf_sb_write(dev_priv, port, cfg1, 0);  in chv_exec_gpio()
385 	u8 gpio_source, gpio_index = 0, gpio_number;  in mipi_exec_gpio()
399 		gpio_source = 0;  in mipi_exec_gpio()
479 	if (intel_dsi->i2c_bus_num < 0) {  in mipi_exec_i2c()
494 	payload_data[0] = reg_offset;  in mipi_exec_i2c()
498 	msg.flags = 0;  in mipi_exec_i2c()
503 	if (ret < 0)  in mipi_exec_i2c()
532 	/* byte 0 aka PMIC Flag is reserved */  in mipi_exec_pmic()
620 		u8 operation_size = 0;  in intel_dsi_vbt_exec()
672 		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);  in intel_dsi_vbt_exec_sequence()
674 		gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0);  in intel_dsi_vbt_exec_sequence()
696 	drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg);  in intel_dsi_log_params()
723 	drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n",  in intel_dsi_log_params()
725 	drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n",  in intel_dsi_log_params()
727 	drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count);  in intel_dsi_log_params()
728 	drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n",  in intel_dsi_log_params()
731 	drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer);  in intel_dsi_log_params()
732 	drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n",  in intel_dsi_log_params()
734 	drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n",  in intel_dsi_log_params()
753 	intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;  in intel_dsi_vbt_init()
754 	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;  in intel_dsi_vbt_init()
772 		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;  in intel_dsi_vbt_init()