93 	for (i = 0; i < 2; i++) {  in rv370_pcie_gart_tlb_flush()
102 #define R300_PTE_UNSNOOPED (1 << 0)
109 		((upper_32_bits(addr) & 0xff) << 24);  in rv370_pcie_gart_get_page_entry()
136 		return 0;  in rv370_pcie_gart_init()
170 	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);  in rv370_pcie_gart_enable()
171 	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);  in rv370_pcie_gart_enable()
176 	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);  in rv370_pcie_gart_enable()
178 	WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);  in rv370_pcie_gart_enable()
184 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",  in rv370_pcie_gart_enable()
188 	return 0;  in rv370_pcie_gart_enable()
195 	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);  in rv370_pcie_gart_disable()
196 	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);  in rv370_pcie_gart_disable()
197 	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);  in rv370_pcie_gart_disable()
198 	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);  in rv370_pcie_gart_disable()
220 	radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));  in r300_fence_ring_emit()
221 	radeon_ring_write(ring, 0);  in r300_fence_ring_emit()
222 	radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));  in r300_fence_ring_emit()
223 	radeon_ring_write(ring, 0);  in r300_fence_ring_emit()
225 	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));  in r300_fence_ring_emit()
227 	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));  in r300_fence_ring_emit()
230 	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));  in r300_fence_ring_emit()
234 	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));  in r300_fence_ring_emit()
237 	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));  in r300_fence_ring_emit()
240 	radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));  in r300_fence_ring_emit()
242 	radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));  in r300_fence_ring_emit()
273 	radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));  in r300_ring_start()
279 	radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));  in r300_ring_start()
281 	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));  in r300_ring_start()
285 	radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));  in r300_ring_start()
287 	radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));  in r300_ring_start()
288 	radeon_ring_write(ring, 0);  in r300_ring_start()
289 	radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));  in r300_ring_start()
290 	radeon_ring_write(ring, 0);  in r300_ring_start()
291 	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));  in r300_ring_start()
293 	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));  in r300_ring_start()
295 	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));  in r300_ring_start()
299 	radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));  in r300_ring_start()
300 	radeon_ring_write(ring, 0);  in r300_ring_start()
301 	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));  in r300_ring_start()
303 	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));  in r300_ring_start()
305 	radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));  in r300_ring_start()
315 	radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));  in r300_ring_start()
324 	radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));  in r300_ring_start()
326 	radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));  in r300_ring_start()
329 	radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));  in r300_ring_start()
338 	rdev->pll_errata = 0;  in r300_errata()
351 	for (i = 0; i < rdev->usec_timeout; i++) {  in r300_mc_wait_for_idle()
355 			return 0;  in r300_mc_wait_for_idle()
366 	if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||  in r300_gpu_init()
367 	    (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {  in r300_gpu_init()
418 	int ret = 0;  in r300_asic_reset()
422 		return 0;  in r300_asic_reset()
426 	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);  in r300_asic_reset()
428 	WREG32(RADEON_CP_CSQ_CNTL, 0);  in r300_asic_reset()
431 	WREG32(RADEON_CP_RB_RPTR_WR, 0);  in r300_asic_reset()
432 	WREG32(RADEON_CP_RB_WPTR, 0);  in r300_asic_reset()
442 	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);  in r300_asic_reset()
445 	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);  in r300_asic_reset()
454 	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);  in r300_asic_reset()
457 	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);  in r300_asic_reset()
484 	case 0: rdev->mc.vram_width = 64; break;  in r300_mc_init()
492 		base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;  in r300_mc_init()
494 	rdev->mc.gtt_base_align = 0;  in r300_mc_init()
513 	case 0:  in rv370_set_pcie_lanes()
554 	while (link_width_cntl == 0xffffffff)  in rv370_set_pcie_lanes()
564 		return 0;  in rv370_get_pcie_lanes()
567 		return 0;  in rv370_get_pcie_lanes()
575 		return 0;  in rv370_get_pcie_lanes()
597 	seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info_show()
599 	seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info_show()
601 	seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info_show()
603 	seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info_show()
605 	seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info_show()
607 	seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info_show()
609 	seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info_show()
610 	return 0;  in rv370_debugfs_pcie_gart_info_show()
633 	uint32_t tmp, tile_flags = 0;  in r300_packet0_check()
647 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",  in r300_packet0_check()
664 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
666 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",  in r300_packet0_check()
677 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
679 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",  in r300_packet0_check()
706 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
708 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",  in r300_packet0_check()
733 	case 0x2084:  in r300_packet0_check()
737 	case 0x20B4:  in r300_packet0_check()
739 		track->vtx_size = idx_value & 0x7F;  in r300_packet0_check()
741 	case 0x2134:  in r300_packet0_check()
743 		track->max_indx = idx_value & 0x00FFFFFFUL;  in r300_packet0_check()
745 	case 0x2088:  in r300_packet0_check()
749 		track->vap_alt_nverts = idx_value & 0xFFFFFF;  in r300_packet0_check()
751 	case 0x43E4:  in r300_packet0_check()
753 		track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;  in r300_packet0_check()
760 	case 0x4E00:  in r300_packet0_check()
767 		track->num_cb = ((idx_value >> 5) & 0x3) + 1;  in r300_packet0_check()
770 	case 0x4E38:  in r300_packet0_check()
771 	case 0x4E3C:  in r300_packet0_check()
772 	case 0x4E40:  in r300_packet0_check()
773 	case 0x4E44:  in r300_packet0_check()
779 			r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
781 				DRM_ERROR("No reloc for ib[%d]=0x%04X\n",  in r300_packet0_check()
794 			tmp = idx_value & ~(0x7 << 16);  in r300_packet0_check()
798 		i = (reg - 0x4E38) >> 2;  in r300_packet0_check()
799 		track->cb[i].pitch = idx_value & 0x3FFE;  in r300_packet0_check()
800 		switch (((idx_value >> 21) & 0xF)) {  in r300_packet0_check()
815 					  ((idx_value >> 21) & 0xF));  in r300_packet0_check()
830 				  ((idx_value >> 21) & 0xF));  in r300_packet0_check()
835 	case 0x4F00:  in r300_packet0_check()
844 	case 0x4F10:  in r300_packet0_check()
846 		switch ((idx_value & 0xF)) {  in r300_packet0_check()
847 		case 0:  in r300_packet0_check()
856 				  (idx_value & 0xF));  in r300_packet0_check()
861 	case 0x4F24:  in r300_packet0_check()
864 			r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
866 				DRM_ERROR("No reloc for ib[%d]=0x%04X\n",  in r300_packet0_check()
879 			tmp = idx_value & ~(0x7 << 16);  in r300_packet0_check()
883 		track->zb.pitch = idx_value & 0x3FFC;  in r300_packet0_check()
886 	case 0x4104:  in r300_packet0_check()
888 		for (i = 0; i < 16; i++) {  in r300_packet0_check()
896 	case 0x44C0:  in r300_packet0_check()
897 	case 0x44C4:  in r300_packet0_check()
898 	case 0x44C8:  in r300_packet0_check()
899 	case 0x44CC:  in r300_packet0_check()
900 	case 0x44D0:  in r300_packet0_check()
901 	case 0x44D4:  in r300_packet0_check()
902 	case 0x44D8:  in r300_packet0_check()
903 	case 0x44DC:  in r300_packet0_check()
904 	case 0x44E0:  in r300_packet0_check()
905 	case 0x44E4:  in r300_packet0_check()
906 	case 0x44E8:  in r300_packet0_check()
907 	case 0x44EC:  in r300_packet0_check()
908 	case 0x44F0:  in r300_packet0_check()
909 	case 0x44F4:  in r300_packet0_check()
910 	case 0x44F8:  in r300_packet0_check()
911 	case 0x44FC:  in r300_packet0_check()
912 		/* TX_FORMAT1_[0-15] */  in r300_packet0_check()
913 		i = (reg - 0x44C0) >> 2;  in r300_packet0_check()
914 		tmp = (idx_value >> 25) & 0x3;  in r300_packet0_check()
916 		switch ((idx_value & 0x1F)) {  in r300_packet0_check()
942 		case 0x17:  in r300_packet0_check()
944 		case 0x1e:  in r300_packet0_check()
965 					  (idx_value & 0x1F));  in r300_packet0_check()
977 				  (idx_value & 0x1F));  in r300_packet0_check()
982 	case 0x4400:  in r300_packet0_check()
983 	case 0x4404:  in r300_packet0_check()
984 	case 0x4408:  in r300_packet0_check()
985 	case 0x440C:  in r300_packet0_check()
986 	case 0x4410:  in r300_packet0_check()
987 	case 0x4414:  in r300_packet0_check()
988 	case 0x4418:  in r300_packet0_check()
989 	case 0x441C:  in r300_packet0_check()
990 	case 0x4420:  in r300_packet0_check()
991 	case 0x4424:  in r300_packet0_check()
992 	case 0x4428:  in r300_packet0_check()
993 	case 0x442C:  in r300_packet0_check()
994 	case 0x4430:  in r300_packet0_check()
995 	case 0x4434:  in r300_packet0_check()
996 	case 0x4438:  in r300_packet0_check()
997 	case 0x443C:  in r300_packet0_check()
998 		/* TX_FILTER0_[0-15] */  in r300_packet0_check()
999 		i = (reg - 0x4400) >> 2;  in r300_packet0_check()
1000 		tmp = idx_value & 0x7;  in r300_packet0_check()
1004 		tmp = (idx_value >> 3) & 0x7;  in r300_packet0_check()
1010 	case 0x4500:  in r300_packet0_check()
1011 	case 0x4504:  in r300_packet0_check()
1012 	case 0x4508:  in r300_packet0_check()
1013 	case 0x450C:  in r300_packet0_check()
1014 	case 0x4510:  in r300_packet0_check()
1015 	case 0x4514:  in r300_packet0_check()
1016 	case 0x4518:  in r300_packet0_check()
1017 	case 0x451C:  in r300_packet0_check()
1018 	case 0x4520:  in r300_packet0_check()
1019 	case 0x4524:  in r300_packet0_check()
1020 	case 0x4528:  in r300_packet0_check()
1021 	case 0x452C:  in r300_packet0_check()
1022 	case 0x4530:  in r300_packet0_check()
1023 	case 0x4534:  in r300_packet0_check()
1024 	case 0x4538:  in r300_packet0_check()
1025 	case 0x453C:  in r300_packet0_check()
1026 		/* TX_FORMAT2_[0-15] */  in r300_packet0_check()
1027 		i = (reg - 0x4500) >> 2;  in r300_packet0_check()
1028 		tmp = idx_value & 0x3FFF;  in r300_packet0_check()
1048 	case 0x4480:  in r300_packet0_check()
1049 	case 0x4484:  in r300_packet0_check()
1050 	case 0x4488:  in r300_packet0_check()
1051 	case 0x448C:  in r300_packet0_check()
1052 	case 0x4490:  in r300_packet0_check()
1053 	case 0x4494:  in r300_packet0_check()
1054 	case 0x4498:  in r300_packet0_check()
1055 	case 0x449C:  in r300_packet0_check()
1056 	case 0x44A0:  in r300_packet0_check()
1057 	case 0x44A4:  in r300_packet0_check()
1058 	case 0x44A8:  in r300_packet0_check()
1059 	case 0x44AC:  in r300_packet0_check()
1060 	case 0x44B0:  in r300_packet0_check()
1061 	case 0x44B4:  in r300_packet0_check()
1062 	case 0x44B8:  in r300_packet0_check()
1063 	case 0x44BC:  in r300_packet0_check()
1064 		/* TX_FORMAT0_[0-15] */  in r300_packet0_check()
1065 		i = (reg - 0x4480) >> 2;  in r300_packet0_check()
1066 		tmp = idx_value & 0x7FF;  in r300_packet0_check()
1068 		tmp = (idx_value >> 11) & 0x7FF;  in r300_packet0_check()
1070 		tmp = (idx_value >> 26) & 0xF;  in r300_packet0_check()
1074 		tmp = (idx_value >> 22) & 0xF;  in r300_packet0_check()
1079 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
1081 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",  in r300_packet0_check()
1088 	case 0x4e0c:  in r300_packet0_check()
1093 	case 0x43a4:  in r300_packet0_check()
1098 			if (idx_value & 0x1)  in r300_packet0_check()
1102 	case 0x4f1c:  in r300_packet0_check()
1115 	case 0x4e04:  in r300_packet0_check()
1121 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
1123 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",  in r300_packet0_check()
1134 		track->aa.pitch = idx_value & 0x3FFE;  in r300_packet0_check()
1138 		track->aaresolve = idx_value & 0x1;  in r300_packet0_check()
1141 	case 0x4f30: /* ZB_MASK_OFFSET */  in r300_packet0_check()
1142 	case 0x4f34: /* ZB_ZMASK_PITCH */  in r300_packet0_check()
1143 	case 0x4f44: /* ZB_HIZ_OFFSET */  in r300_packet0_check()
1144 	case 0x4f54: /* ZB_HIZ_PITCH */  in r300_packet0_check()
1148 	case 0x4028:  in r300_packet0_check()
1156 	case 0x4be8:  in r300_packet0_check()
1165 	return 0;  in r300_packet0_check()
1167 	pr_err("Forbidden register 0x%04X in cs at %d (val=%08x)\n",  in r300_packet0_check()
1191 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet3_check()
1208 		if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {  in r300_packet3_check()
1223 		if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {  in r300_packet3_check()
1277 	return 0;  in r300_packet3_check()
1317 	return 0;  in r300_cs_parse()
1340 			upper_32_bits(rdev->mc.agp_base) & 0xff);  in r300_mc_program()
1342 		WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);  in r300_mc_program()
1343 		WREG32(R_000170_AGP_BASE, 0);  in r300_mc_program()
1344 		WREG32(R_00015C_AGP_BASE_2, 0);  in r300_mc_program()
1434 	return 0;  in r300_startup()
1450 		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",  in r300_resume()
1479 	return 0;  in r300_suspend()
1531 			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",  in r300_init()
1588 	return 0;  in r300_init()