Searched +full:0 +full:x4094 (Results 1 – 21 of 21) sorted by relevance
| /Linux-v5.15/drivers/remoteproc/ |
| D | mtk_common.h | 15 #define MT8183_SW_RSTN 0x0 16 #define MT8183_SW_RSTN_BIT BIT(0) 17 #define MT8183_SCP_TO_HOST 0x1C 18 #define MT8183_SCP_IPC_INT_BIT BIT(0) 20 #define MT8183_HOST_TO_SCP 0x28 21 #define MT8183_HOST_IPC_INT_BIT BIT(0) 22 #define MT8183_WDT_CFG 0x84 23 #define MT8183_SCP_CLK_SW_SEL 0x4000 24 #define MT8183_SCP_CLK_DIV_SEL 0x4024 25 #define MT8183_SCP_SRAM_PDN 0x402C [all …]
|
| /Linux-v5.15/Documentation/devicetree/bindings/mfd/ |
| D | ti,j721e-system-controller.yaml | 46 "^mux-controller@[0-9a-f]+$": 64 reg = <0x00100000 0x1c000>; 71 reg = <0x00004080 0x50>; 75 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 76 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 77 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 78 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 79 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
|
| /Linux-v5.15/include/linux/mfd/wm831x/ |
| D | core.h | 25 #define WM831X_RESET_ID 0x00 26 #define WM831X_REVISION 0x01 27 #define WM831X_PARENT_ID 0x4000 28 #define WM831X_SYSVDD_CONTROL 0x4001 29 #define WM831X_THERMAL_MONITORING 0x4002 30 #define WM831X_POWER_STATE 0x4003 31 #define WM831X_WATCHDOG 0x4004 32 #define WM831X_ON_PIN_CONTROL 0x4005 33 #define WM831X_RESET_CONTROL 0x4006 34 #define WM831X_CONTROL_INTERFACE 0x4007 [all …]
|
| /Linux-v5.15/drivers/gpu/drm/radeon/reg_srcs/ |
| D | rv515 | 1 rv515 0x6d40 2 0x1434 SRC_Y_X 3 0x1438 DST_Y_X 4 0x143C DST_HEIGHT_WIDTH 5 0x146C DP_GUI_MASTER_CNTL 6 0x1474 BRUSH_Y_X 7 0x1478 DP_BRUSH_BKGD_CLR 8 0x147C DP_BRUSH_FRGD_CLR 9 0x1480 BRUSH_DATA0 10 0x1484 BRUSH_DATA1 [all …]
|
| /Linux-v5.15/drivers/net/ethernet/agere/ |
| D | et131x.h | 53 #define LBCIF_DWORD0_GROUP 0xAC 54 #define LBCIF_DWORD1_GROUP 0xB0 57 #define LBCIF_ADDRESS_REGISTER 0xAC 58 #define LBCIF_DATA_REGISTER 0xB0 59 #define LBCIF_CONTROL_REGISTER 0xB1 60 #define LBCIF_STATUS_REGISTER 0xB2 63 #define LBCIF_CONTROL_SEQUENTIAL_READ 0x01 64 #define LBCIF_CONTROL_PAGE_WRITE 0x02 65 #define LBCIF_CONTROL_EEPROM_RELOAD 0x08 66 #define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20 [all …]
|
| /Linux-v5.15/drivers/net/wireless/ath/ath9k/ |
| D | reg.h | 22 #define AR_CR 0x0008 23 #define AR_CR_RXE (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004) 24 #define AR_CR_RXD 0x00000020 25 #define AR_CR_SWI 0x00000040 27 #define AR_RXDP 0x000C 29 #define AR_CFG 0x0014 30 #define AR_CFG_SWTD 0x00000001 31 #define AR_CFG_SWTB 0x00000002 32 #define AR_CFG_SWRD 0x00000004 33 #define AR_CFG_SWRB 0x00000008 [all …]
|
| /Linux-v5.15/drivers/media/dvb-frontends/ |
| D | ds3000.c | 27 } while (0) 37 0x23, 0x05, 38 0x08, 0x03, 39 0x0c, 0x00, 40 0x21, 0x54, 41 0x25, 0x82, 42 0x27, 0x31, 43 0x30, 0x08, 44 0x31, 0x40, 45 0x32, 0x32, [all …]
|
| /Linux-v5.15/arch/arm/boot/dts/ |
| D | qcom-apq8064.dtsi | 24 reg = <0x80000000 0x200000>; 29 reg = <0x8f000000 0x700000>; 36 #size-cells = <0>; 38 CPU0: cpu@0 { 42 reg = <0>; 100 reg = <0x0 0x0>; 109 coefficients = <1199 0>; 130 coefficients = <1132 0>; 151 coefficients = <1199 0>; 172 coefficients = <1132 0>; [all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/powerpc/power9/ |
| D | other.json | 3 "EventCode": "0x3084", 8 "EventCode": "0xF880", 13 "EventCode": "0x4088", 18 "EventCode": "0x20A4", 23 "EventCode": "0x40008", 28 "EventCode": "0x20064", 33 "EventCode": "0x260B4", 38 "EventCode": "0x20006", 43 "EventCode": "0x201E4", 48 "EventCode": "0x4E044", [all …]
|
| /Linux-v5.15/arch/arm64/boot/dts/ti/ |
| D | k3-j721e-main.dtsi | 13 #clock-cells = <0>; 15 clock-frequency = <0>; 19 #clock-cells = <0>; 21 clock-frequency = <0>; 28 reg = <0x0 0x70000000 0x0 0x800000>; 31 ranges = <0x0 0x0 0x70000000 0x800000>; 33 atf-sram@0 { 34 reg = <0x0 0x20000>; 40 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 43 ranges = <0x0 0x0 0x00100000 0x1c000>; [all …]
|
| /Linux-v5.15/sound/soc/mediatek/mt8195/ |
| D | mt8195-reg.h | 13 #define AFE_SRAM_BASE (0x10880000) 14 #define AFE_SRAM_SIZE (0x10000) 16 #define AUDIO_TOP_CON0 (0x0000) 17 #define AUDIO_TOP_CON1 (0x0004) 18 #define AUDIO_TOP_CON2 (0x0008) 19 #define AUDIO_TOP_CON3 (0x000c) 20 #define AUDIO_TOP_CON4 (0x0010) 21 #define AUDIO_TOP_CON5 (0x0014) 22 #define AUDIO_TOP_CON6 (0x0018) 23 #define AFE_MAS_HADDR_MSB (0x0020) [all …]
|
| /Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dce/ |
| D | dce_6_0_d.h | 26 #define ixATTR00 0x0000 27 #define ixATTR01 0x0001 28 #define ixATTR02 0x0002 29 #define ixATTR03 0x0003 30 #define ixATTR04 0x0004 31 #define ixATTR05 0x0005 32 #define ixATTR06 0x0006 33 #define ixATTR07 0x0007 34 #define ixATTR08 0x0008 35 #define ixATTR09 0x0009 [all …]
|
| D | dce_8_0_d.h | 27 #define mmPIPE0_PG_CONFIG 0x1760 28 #define mmPIPE0_PG_ENABLE 0x1761 29 #define mmPIPE0_PG_STATUS 0x1762 30 #define mmPIPE1_PG_CONFIG 0x1764 31 #define mmPIPE1_PG_ENABLE 0x1765 32 #define mmPIPE1_PG_STATUS 0x1766 33 #define mmPIPE2_PG_CONFIG 0x1768 34 #define mmPIPE2_PG_ENABLE 0x1769 35 #define mmPIPE2_PG_STATUS 0x176a 36 #define mmPIPE3_PG_CONFIG 0x176c [all …]
|
| D | dce_11_0_d.h | 27 #define mmPIPE0_PG_CONFIG 0x2c0 28 #define mmPIPE0_PG_ENABLE 0x2c1 29 #define mmPIPE0_PG_STATUS 0x2c2 30 #define mmPIPE1_PG_CONFIG 0x2c3 31 #define mmPIPE1_PG_ENABLE 0x2c4 32 #define mmPIPE1_PG_STATUS 0x2c5 33 #define mmPIPE2_PG_CONFIG 0x2c6 34 #define mmPIPE2_PG_ENABLE 0x2c7 35 #define mmPIPE2_PG_STATUS 0x2c8 36 #define mmDCFEV0_PG_CONFIG 0x2db [all …]
|
| D | dce_10_0_d.h | 27 #define mmPIPE0_PG_CONFIG 0x2c0 28 #define mmPIPE0_PG_ENABLE 0x2c1 29 #define mmPIPE0_PG_STATUS 0x2c2 30 #define mmPIPE1_PG_CONFIG 0x2c3 31 #define mmPIPE1_PG_ENABLE 0x2c4 32 #define mmPIPE1_PG_STATUS 0x2c5 33 #define mmPIPE2_PG_CONFIG 0x2c6 34 #define mmPIPE2_PG_ENABLE 0x2c7 35 #define mmPIPE2_PG_STATUS 0x2c8 36 #define mmPIPE3_PG_CONFIG 0x2c9 [all …]
|
| D | dce_11_2_d.h | 27 #define mmPIPE0_PG_CONFIG 0x2c0 28 #define mmPIPE0_PG_ENABLE 0x2c1 29 #define mmPIPE0_PG_STATUS 0x2c2 30 #define mmPIPE1_PG_CONFIG 0x2c3 31 #define mmPIPE1_PG_ENABLE 0x2c4 32 #define mmPIPE1_PG_STATUS 0x2c5 33 #define mmPIPE2_PG_CONFIG 0x2c6 34 #define mmPIPE2_PG_ENABLE 0x2c7 35 #define mmPIPE2_PG_STATUS 0x2c8 36 #define mmPIPE3_PG_CONFIG 0x2c9 [all …]
|
| /Linux-v5.15/drivers/net/ethernet/sun/ |
| D | cassini.h | 8 * vendor id: 0x108E (Sun Microsystems, Inc.) 9 * device id: 0xabba (Cassini) 10 * revision ids: 0x01 = Cassini 11 * 0x02 = Cassini rev 2 12 * 0x10 = Cassini+ 13 * 0x11 = Cassini+ 0.2u 15 * vendor id: 0x100b (National Semiconductor) 16 * device id: 0x0035 (DP83065/Saturn) 17 * revision ids: 0x30 = Saturn B2 19 * rings are all offset from 0. [all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | other.json | 3 "EventCode": "0x1f05e", 9 "EventCode": "0x2006e", 11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to … 15 "EventCode": "0x4e05e", 17 …"BriefDescription": "Number of cycles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 bel… 21 "EventCode": "0x610050", 27 "EventCode": "0x520050", 33 "EventCode": "0x620052", 39 "EventCode": "0x610052", 45 "EventCode": "0x610054", [all …]
|
| /Linux-v5.15/drivers/gpu/drm/i915/gvt/ |
| D | handlers.c | 45 #define PCH_PP_STATUS _MMIO(0xc7200) 46 #define PCH_PP_CONTROL _MMIO(0xc7204) 47 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 48 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 49 #define PCH_PP_DIVISOR _MMIO(0xc7210) 66 return 0; in intel_gvt_get_device_type() 108 return 0; in new_mmio_info() 144 return 0; in new_mmio_info() 161 offset &= ~GENMASK(11, 0); in intel_gvt_render_mmio_to_engine() 170 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) [all …]
|
| /Linux-v5.15/drivers/gpu/drm/i915/ |
| D | i915_reg.h | 106 * #define _FOO_A 0xf000 107 * #define _FOO_B 0xf001 111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 115 * #define BAR _MMIO(0xb000) 116 * #define GEN8_BAR _MMIO(0xb888) 121 * @__n: 0-based bit number 130 ((__n) < 0 || (__n) > 31)))) 134 * @__high: 0-based high bit 135 * @__low: 0-based low bit 145 ((__low) < 0 || (__high) > 31 || (__low) > (__high))))) [all …]
|
| /Linux-v5.15/drivers/net/wireless/realtek/rtw88/ |
| D | rtw8822c_table.c | 16 0x83000000, 0x00000000, 0x40000000, 0x00000000, 17 0x1D90, 0x300001FF, 18 0x1D90, 0x300101FE, 19 0x1D90, 0x300201FD, 20 0x1D90, 0x300301FC, 21 0x1D90, 0x300401FB, 22 0x1D90, 0x300501FA, 23 0x1D90, 0x300601F9, 24 0x1D90, 0x300701F8, 25 0x1D90, 0x300801F7, [all …]
|