Lines Matching +full:0 +full:x4094
45 #define PCH_PP_STATUS _MMIO(0xc7200)
46 #define PCH_PP_CONTROL _MMIO(0xc7204)
47 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
48 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
49 #define PCH_PP_DIVISOR _MMIO(0xc7210)
66 return 0; in intel_gvt_get_device_type()
108 return 0; in new_mmio_info()
144 return 0; in new_mmio_info()
161 offset &= ~GENMASK(11, 0); in intel_gvt_render_mmio_to_engine()
170 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
173 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
212 memset(p_data, 0, bytes); in sanitize_fence_mmio_access()
215 return 0; in sanitize_fence_mmio_access()
240 return 0; in gamw_echo_dev_rw_ia_write()
253 return 0; in fence_mmio_read()
272 return 0; in fence_mmio_write()
277 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
302 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); in mul_force_wake_write()
310 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); in mul_force_wake_write()
311 return 0; in mul_force_wake_write()
317 intel_engine_mask_t engine_mask = 0; in gdrst_mmio_write()
358 vgpu_vreg(vgpu, offset) = 0; in gdrst_mmio_write()
360 return 0; in gdrst_mmio_write()
390 return 0; in pch_pp_control_mmio_write()
402 return 0; in transconf_mmio_write()
420 return 0; in lcpll_ctl_mmio_write()
427 case 0xe651c: in dpy_reg_mmio_read()
428 case 0xe661c: in dpy_reg_mmio_read()
429 case 0xe671c: in dpy_reg_mmio_read()
430 case 0xe681c: in dpy_reg_mmio_read()
433 case 0xe6c04: in dpy_reg_mmio_read()
434 vgpu_vreg(vgpu, offset) = 0x3; in dpy_reg_mmio_read()
436 case 0xe6e1c: in dpy_reg_mmio_read()
437 vgpu_vreg(vgpu, offset) = 0x2f << 16; in dpy_reg_mmio_read()
444 return 0; in dpy_reg_mmio_read()
465 u32 dp_br = 0; in bdw_vgpu_get_dp_bitrate()
491 gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n", in bdw_vgpu_get_dp_bitrate()
516 gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n", in bdw_vgpu_get_dp_bitrate()
529 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n", in bdw_vgpu_get_dp_bitrate()
540 u32 dp_br = 0; in bxt_vgpu_get_dp_bitrate()
544 struct dpll clock = {0}; in bxt_vgpu_get_dp_bitrate()
568 gvt_dbg_dpy("vgpu-%d PORT_%c PLL_ENABLE 0x%08x isn't enabled or locked\n", in bxt_vgpu_get_dp_bitrate()
574 clock.m2 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0)) & PORT_PLL_M2_MASK) << 22; in bxt_vgpu_get_dp_bitrate()
583 if (clock.n == 0 || clock.p == 0) { in bxt_vgpu_get_dp_bitrate()
599 u32 dp_br = 0; in skl_vgpu_get_dp_bitrate()
637 dp_br = 0; in skl_vgpu_get_dp_bitrate()
676 u64 pixel_clk = 0; in vgpu_update_refresh_rate()
677 u32 new_rate = 0; in vgpu_update_refresh_rate()
685 …new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal… in vgpu_update_refresh_rate()
711 return 0; in pipeconf_mmio_write()
716 _MMIO(0xd80),
717 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
718 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
719 CL_PRIMITIVES_COUNT, //_MMIO(0x2340)
720 PS_INVOCATION_COUNT, //_MMIO(0x2348)
721 PS_DEPTH_COUNT, //_MMIO(0x2350)
722 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
723 _MMIO(0x2690),
724 _MMIO(0x2694),
725 _MMIO(0x2698),
726 _MMIO(0x2754),
727 _MMIO(0x28a0),
728 _MMIO(0x4de0),
729 _MMIO(0x4de4),
730 _MMIO(0x4dfc),
731 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
732 _MMIO(0x7014),
733 HDC_CHICKEN0,//_MMIO(0x7300)
734 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
735 _MMIO(0x7700),
736 _MMIO(0x7704),
737 _MMIO(0x7708),
738 _MMIO(0x770c),
739 _MMIO(0x83a8),
740 _MMIO(0xb110),
741 GEN8_L3SQCREG4,//_MMIO(0xb118)
742 _MMIO(0xe100),
743 _MMIO(0xe18c),
744 _MMIO(0xe48c),
745 _MMIO(0xe5f4),
746 _MMIO(0x64844),
752 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); in in_whitelist()
788 return 0; in force_nonpriv_write()
804 return 0; in ddi_buf_ctl_mmio_write()
811 return 0; in fdi_rx_iir_mmio_write()
814 #define FDI_LINK_TRAIN_PATTERN1 0
830 return 0; in fdi_auto_training_started()
863 return 0; in check_fdi_rx_train_status()
871 return 0; in check_fdi_rx_train_status()
874 #define INVALID_INDEX (~0U)
890 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
893 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
896 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
921 if (ret < 0) in update_fdi_rx_iir_status()
927 if (ret < 0) in update_fdi_rx_iir_status()
936 return 0; in update_fdi_rx_iir_status()
940 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
953 if (data == 0x2) { in dp_tp_ctl_mmio_write()
957 return 0; in dp_tp_ctl_mmio_write()
972 return 0; in dp_tp_status_mmio_write()
985 return 0; in pch_adpa_mmio_write()
1000 return 0; in south_chicken2_mmio_write()
1004 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
1023 return 0; in pri_surf_mmio_write()
1027 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
1043 return 0; in spr_surf_mmio_write()
1068 return 0; in reg50080_mmio_write()
1094 return 0; in trigger_aux_channel_interrupt()
1111 value &= ~(0xf << 20); in dp_aux_ch_ctl_trans_done()
1117 return 0; in dp_aux_ch_ctl_trans_done()
1150 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
1152 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
1154 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
1171 return 0; in dp_aux_ch_ctl_mmio_write()
1180 return 0; in dp_aux_ch_ctl_mmio_write()
1184 return 0; in dp_aux_ch_ctl_mmio_write()
1189 vgpu_vreg(vgpu, offset) = 0; in dp_aux_ch_ctl_mmio_write()
1190 return 0; in dp_aux_ch_ctl_mmio_write()
1198 addr = (msg >> 8) & 0xffff; in dp_aux_ch_ctl_mmio_write()
1199 ctrl = (msg >> 24) & 0xff; in dp_aux_ch_ctl_mmio_write()
1200 len = msg & 0xff; in dp_aux_ch_ctl_mmio_write()
1219 return 0; in dp_aux_ch_ctl_mmio_write()
1233 for (t = 0; t < 4; t++) { in dp_aux_ch_ctl_mmio_write()
1236 buf[t * 4] = (r >> 24) & 0xff; in dp_aux_ch_ctl_mmio_write()
1237 buf[t * 4 + 1] = (r >> 16) & 0xff; in dp_aux_ch_ctl_mmio_write()
1238 buf[t * 4 + 2] = (r >> 8) & 0xff; in dp_aux_ch_ctl_mmio_write()
1239 buf[t * 4 + 3] = r & 0xff; in dp_aux_ch_ctl_mmio_write()
1244 for (t = 0; t <= len; t++) { in dp_aux_ch_ctl_mmio_write()
1256 vgpu_vreg(vgpu, offset + 4) = 0; in dp_aux_ch_ctl_mmio_write()
1259 return 0; in dp_aux_ch_ctl_mmio_write()
1263 int idx, i, ret = 0; in dp_aux_ch_ctl_mmio_write()
1275 vgpu_vreg(vgpu, offset + 4) = 0; in dp_aux_ch_ctl_mmio_write()
1276 vgpu_vreg(vgpu, offset + 8) = 0; in dp_aux_ch_ctl_mmio_write()
1277 vgpu_vreg(vgpu, offset + 12) = 0; in dp_aux_ch_ctl_mmio_write()
1278 vgpu_vreg(vgpu, offset + 16) = 0; in dp_aux_ch_ctl_mmio_write()
1279 vgpu_vreg(vgpu, offset + 20) = 0; in dp_aux_ch_ctl_mmio_write()
1283 return 0; in dp_aux_ch_ctl_mmio_write()
1288 vgpu_vreg(vgpu, offset + 4 * idx) = 0; in dp_aux_ch_ctl_mmio_write()
1312 ret = 0; in dp_aux_ch_ctl_mmio_write()
1318 return 0; in dp_aux_ch_ctl_mmio_write()
1326 return 0; in dp_aux_ch_ctl_mmio_write()
1334 return 0; in mbctl_write()
1347 return 0; in vga_control_mmio_write()
1357 for (i = 0; i < num; ++i) in read_virtual_sbi_register()
1362 return 0; in read_virtual_sbi_register()
1374 for (i = 0; i < num; ++i) { in write_virtual_sbi_register()
1402 return 0; in sbi_data_mmio_read()
1429 return 0; in sbi_ctl_mmio_write()
1453 case 0x78010: /* vgt_caps */ in pvinfo_mmio_read()
1454 case 0x7881c: in pvinfo_mmio_read()
1464 return 0; in pvinfo_mmio_read()
1473 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); in handle_g2v_notification()
1492 return 0; in handle_g2v_notification()
1503 env[0] = display_ready_str; in send_display_ready_uevent()
1519 send_display_ready_uevent(vgpu, data ? 1 : 0); in pvinfo_mmio_write()
1527 case _vgtif_reg(pdp[0].lo): in pvinfo_mmio_write()
1528 case _vgtif_reg(pdp[0].hi): in pvinfo_mmio_write()
1538 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): in pvinfo_mmio_write()
1552 return 0; in pvinfo_mmio_write()
1563 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { in pf_write()
1567 return 0; in pf_write()
1585 return 0; in power_well_ctl_mmio_write()
1598 return 0; in gen9_dbuf_ctl_mmio_write()
1608 return 0; in fpga_dbg_mmio_write()
1624 return 0; in dma_ctrl_write()
1627 return 0; in dma_ctrl_write()
1636 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { in gen9_trtte_write()
1644 return 0; in gen9_trtte_write()
1651 return 0; in gen9_trtt_chicken_write()
1657 u32 v = 0; in dpll_status_read()
1659 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) in dpll_status_read()
1660 v |= (1 << 0); in dpll_status_read()
1662 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) in dpll_status_read()
1665 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) in dpll_status_read()
1668 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) in dpll_status_read()
1680 u32 cmd = value & 0xff; in mailbox_write()
1695 *data0 = 0x1e1a1100; in mailbox_write()
1697 *data0 = 0x61514b3d; in mailbox_write()
1705 *data0 = 0x16080707; in mailbox_write()
1707 *data0 = 0x16161616; in mailbox_write()
1718 *data0 |= 0x1; in mailbox_write()
1741 if (value != 0 && in hws_pga_write()
1743 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", in hws_pga_write()
1754 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", in hws_pga_write()
1759 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", in hws_pga_write()
1791 return 0; in skl_lcpll_write()
1804 return 0; in bxt_de_pll_enable_write()
1817 return 0; in bxt_port_pll_enable_write()
1824 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0; in bxt_phy_ctl_family_write()
1838 return 0; in bxt_phy_ctl_family_write()
1859 vgpu_vreg(vgpu, offset - 0x600) = v; in bxt_pcs_dw12_grp_write()
1860 vgpu_vreg(vgpu, offset - 0x800) = v; in bxt_pcs_dw12_grp_write()
1862 vgpu_vreg(vgpu, offset - 0x400) = v; in bxt_pcs_dw12_grp_write()
1863 vgpu_vreg(vgpu, offset - 0x600) = v; in bxt_pcs_dw12_grp_write()
1868 return 0; in bxt_pcs_dw12_grp_write()
1876 if (v & BIT(0)) { in bxt_gt_disp_pwron_write()
1893 return 0; in bxt_gt_disp_pwron_write()
1899 vgpu_vreg(vgpu, offset) = 0; in edp_psr_imr_iir_write()
1900 return 0; in edp_psr_imr_iir_write()
1910 * PML4 PTE: PAT(0) PCD(1) PWT(1).
1917 GEN8_PPAT(0, CHV_PPAT_SNOOP) | in bxt_ppat_low_write()
1918 GEN8_PPAT(1, 0) | in bxt_ppat_low_write()
1919 GEN8_PPAT(2, 0) | in bxt_ppat_low_write()
1928 return 0; in bxt_ppat_low_write()
1938 return 0; in guc_status_read()
1975 int ret = 0; in elsp_mmio_write()
2006 execlist->elsp_dwords.index &= 0x3; in elsp_mmio_write()
2027 return 0; in ring_mode_mmio_write()
2034 return 0; in ring_mode_mmio_write()
2045 return 0; in ring_mode_mmio_write()
2056 return 0; in ring_mode_mmio_write()
2066 return 0; in ring_mode_mmio_write()
2072 unsigned int id = 0; in gvt_reg_tlb_control_handler()
2075 vgpu_vreg(vgpu, offset) = 0; in gvt_reg_tlb_control_handler()
2078 case 0x4260: in gvt_reg_tlb_control_handler()
2081 case 0x4264: in gvt_reg_tlb_control_handler()
2084 case 0x4268: in gvt_reg_tlb_control_handler()
2087 case 0x426c: in gvt_reg_tlb_control_handler()
2090 case 0x4270: in gvt_reg_tlb_control_handler()
2098 return 0; in gvt_reg_tlb_control_handler()
2115 return 0; in ring_reset_ctl_write()
2124 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); in csfe_chicken1_mmio_write()
2127 if (IS_MASKED_BITS_ENABLED(data, 0x10) || in csfe_chicken1_mmio_write()
2128 IS_MASKED_BITS_ENABLED(data, 0x8)) in csfe_chicken1_mmio_write()
2131 return 0; in csfe_chicken1_mmio_write()
2139 } while (0)
2142 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
2145 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
2148 MMIO_F(reg, 4, f, 0, 0, d, r, w)
2151 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
2154 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
2157 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
2166 } while (0)
2169 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
2172 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
2175 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
2178 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
2181 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
2188 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, in init_generic_mmio_info()
2191 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); in init_generic_mmio_info()
2192 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); in init_generic_mmio_info()
2193 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); in init_generic_mmio_info()
2196 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL); in init_generic_mmio_info()
2206 #define RING_REG(base) _MMIO((base) + 0x28) in init_generic_mmio_info()
2210 #define RING_REG(base) _MMIO((base) + 0x134) in init_generic_mmio_info()
2214 #define RING_REG(base) _MMIO((base) + 0x6c) in init_generic_mmio_info()
2215 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); in init_generic_mmio_info()
2219 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); in init_generic_mmio_info()
2221 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); in init_generic_mmio_info()
2224 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL); in init_generic_mmio_info()
2225 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL); in init_generic_mmio_info()
2226 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL); in init_generic_mmio_info()
2227 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL); in init_generic_mmio_info()
2231 #define RING_REG(base) _MMIO((base) + 0x29c) in init_generic_mmio_info()
2251 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2253 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2255 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2258 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2264 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2265 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2266 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2267 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2268 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2269 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2270 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2271 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2276 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2277 MMIO_D(_MMIO(0x602a0), D_ALL); in init_generic_mmio_info()
2279 MMIO_D(_MMIO(0x65050), D_ALL); in init_generic_mmio_info()
2280 MMIO_D(_MMIO(0x650b4), D_ALL); in init_generic_mmio_info()
2282 MMIO_D(_MMIO(0xc4040), D_ALL); in init_generic_mmio_info()
2326 MMIO_D(_MMIO(0x700ac), D_ALL); in init_generic_mmio_info()
2327 MMIO_D(_MMIO(0x710ac), D_ALL); in init_generic_mmio_info()
2328 MMIO_D(_MMIO(0x720ac), D_ALL); in init_generic_mmio_info()
2330 MMIO_D(_MMIO(0x70090), D_ALL); in init_generic_mmio_info()
2331 MMIO_D(_MMIO(0x70094), D_ALL); in init_generic_mmio_info()
2332 MMIO_D(_MMIO(0x70098), D_ALL); in init_generic_mmio_info()
2333 MMIO_D(_MMIO(0x7009c), D_ALL); in init_generic_mmio_info()
2521 MMIO_D(_MMIO(0x48268), D_ALL); in init_generic_mmio_info()
2523 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, in init_generic_mmio_info()
2525 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2526 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2528 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, in init_generic_mmio_info()
2530 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, in init_generic_mmio_info()
2532 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, in init_generic_mmio_info()
2612 MMIO_D(_MMIO(0x61208), D_ALL); in init_generic_mmio_info()
2613 MMIO_D(_MMIO(0x6120c), D_ALL); in init_generic_mmio_info()
2617 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); in init_generic_mmio_info()
2618 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); in init_generic_mmio_info()
2619 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); in init_generic_mmio_info()
2620 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); in init_generic_mmio_info()
2621 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); in init_generic_mmio_info()
2622 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); in init_generic_mmio_info()
2624 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, in init_generic_mmio_info()
2704 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2708 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2712 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2714 MMIO_D(_MMIO(0x60110), D_ALL); in init_generic_mmio_info()
2715 MMIO_D(_MMIO(0x61110), D_ALL); in init_generic_mmio_info()
2716 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2717 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2718 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2719 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); in init_generic_mmio_info()
2720 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); in init_generic_mmio_info()
2721 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); in init_generic_mmio_info()
2722 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); in init_generic_mmio_info()
2723 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); in init_generic_mmio_info()
2724 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); in init_generic_mmio_info()
2742 MMIO_D(_MMIO(0x46508), D_ALL); in init_generic_mmio_info()
2744 MMIO_D(_MMIO(0x49080), D_ALL); in init_generic_mmio_info()
2745 MMIO_D(_MMIO(0x49180), D_ALL); in init_generic_mmio_info()
2746 MMIO_D(_MMIO(0x49280), D_ALL); in init_generic_mmio_info()
2748 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2749 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2750 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2770 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, in init_generic_mmio_info()
2791 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2792 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2793 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2794 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2795 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2860 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); in init_generic_mmio_info()
2868 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2871 MMIO_D(_MMIO(0x13812c), D_ALL); in init_generic_mmio_info()
2877 MMIO_D(_MMIO(0x3c), D_ALL); in init_generic_mmio_info()
2878 MMIO_D(_MMIO(0x860), D_ALL); in init_generic_mmio_info()
2880 MMIO_D(_MMIO(0x121d0), D_ALL); in init_generic_mmio_info()
2882 MMIO_D(_MMIO(0x41d0), D_ALL); in init_generic_mmio_info()
2884 MMIO_D(_MMIO(0x6200), D_ALL); in init_generic_mmio_info()
2885 MMIO_D(_MMIO(0x6204), D_ALL); in init_generic_mmio_info()
2886 MMIO_D(_MMIO(0x6208), D_ALL); in init_generic_mmio_info()
2887 MMIO_D(_MMIO(0x7118), D_ALL); in init_generic_mmio_info()
2888 MMIO_D(_MMIO(0x7180), D_ALL); in init_generic_mmio_info()
2889 MMIO_D(_MMIO(0x7408), D_ALL); in init_generic_mmio_info()
2890 MMIO_D(_MMIO(0x7c00), D_ALL); in init_generic_mmio_info()
2892 MMIO_D(_MMIO(0x911c), D_ALL); in init_generic_mmio_info()
2893 MMIO_D(_MMIO(0x9120), D_ALL); in init_generic_mmio_info()
2897 MMIO_D(_MMIO(0x48800), D_ALL); in init_generic_mmio_info()
2898 MMIO_D(_MMIO(0xce044), D_ALL); in init_generic_mmio_info()
2899 MMIO_D(_MMIO(0xe6500), D_ALL); in init_generic_mmio_info()
2900 MMIO_D(_MMIO(0xe6504), D_ALL); in init_generic_mmio_info()
2901 MMIO_D(_MMIO(0xe6600), D_ALL); in init_generic_mmio_info()
2902 MMIO_D(_MMIO(0xe6604), D_ALL); in init_generic_mmio_info()
2903 MMIO_D(_MMIO(0xe6700), D_ALL); in init_generic_mmio_info()
2904 MMIO_D(_MMIO(0xe6704), D_ALL); in init_generic_mmio_info()
2905 MMIO_D(_MMIO(0xe6800), D_ALL); in init_generic_mmio_info()
2906 MMIO_D(_MMIO(0xe6804), D_ALL); in init_generic_mmio_info()
2910 MMIO_D(_MMIO(0x902c), D_ALL); in init_generic_mmio_info()
2911 MMIO_D(_MMIO(0xec008), D_ALL); in init_generic_mmio_info()
2912 MMIO_D(_MMIO(0xec00c), D_ALL); in init_generic_mmio_info()
2913 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL); in init_generic_mmio_info()
2914 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL); in init_generic_mmio_info()
2915 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL); in init_generic_mmio_info()
2916 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL); in init_generic_mmio_info()
2917 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL); in init_generic_mmio_info()
2918 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL); in init_generic_mmio_info()
2919 MMIO_D(_MMIO(0xec408), D_ALL); in init_generic_mmio_info()
2920 MMIO_D(_MMIO(0xec40c), D_ALL); in init_generic_mmio_info()
2921 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL); in init_generic_mmio_info()
2922 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL); in init_generic_mmio_info()
2923 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL); in init_generic_mmio_info()
2924 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL); in init_generic_mmio_info()
2925 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL); in init_generic_mmio_info()
2926 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL); in init_generic_mmio_info()
2927 MMIO_D(_MMIO(0xfc810), D_ALL); in init_generic_mmio_info()
2928 MMIO_D(_MMIO(0xfc81c), D_ALL); in init_generic_mmio_info()
2929 MMIO_D(_MMIO(0xfc828), D_ALL); in init_generic_mmio_info()
2930 MMIO_D(_MMIO(0xfc834), D_ALL); in init_generic_mmio_info()
2931 MMIO_D(_MMIO(0xfcc00), D_ALL); in init_generic_mmio_info()
2932 MMIO_D(_MMIO(0xfcc0c), D_ALL); in init_generic_mmio_info()
2933 MMIO_D(_MMIO(0xfcc18), D_ALL); in init_generic_mmio_info()
2934 MMIO_D(_MMIO(0xfcc24), D_ALL); in init_generic_mmio_info()
2935 MMIO_D(_MMIO(0xfd000), D_ALL); in init_generic_mmio_info()
2936 MMIO_D(_MMIO(0xfd00c), D_ALL); in init_generic_mmio_info()
2937 MMIO_D(_MMIO(0xfd018), D_ALL); in init_generic_mmio_info()
2938 MMIO_D(_MMIO(0xfd024), D_ALL); in init_generic_mmio_info()
2939 MMIO_D(_MMIO(0xfd034), D_ALL); in init_generic_mmio_info()
2942 MMIO_D(_MMIO(0x2054), D_ALL); in init_generic_mmio_info()
2943 MMIO_D(_MMIO(0x12054), D_ALL); in init_generic_mmio_info()
2944 MMIO_D(_MMIO(0x22054), D_ALL); in init_generic_mmio_info()
2945 MMIO_D(_MMIO(0x1a054), D_ALL); in init_generic_mmio_info()
2947 MMIO_D(_MMIO(0x44070), D_ALL); in init_generic_mmio_info()
2948 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2949 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2950 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2951 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2952 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2954 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); in init_generic_mmio_info()
2955 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS); in init_generic_mmio_info()
2956 MMIO_D(_MMIO(0x2360), D_BDW_PLUS); in init_generic_mmio_info()
2957 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2958 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2959 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2961 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2962 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2965 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2966 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2967 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2968 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2969 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2970 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2971 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2972 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2973 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2974 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2975 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2976 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); in init_generic_mmio_info()
2977 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); in init_generic_mmio_info()
2978 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); in init_generic_mmio_info()
2979 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); in init_generic_mmio_info()
2980 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); in init_generic_mmio_info()
2981 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2985 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2986 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2987 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2990 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2991 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2992 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2993 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2999 return 0; in init_generic_mmio_info()
3007 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); in init_bdw_mmio_info()
3008 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); in init_bdw_mmio_info()
3009 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); in init_bdw_mmio_info()
3010 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); in init_bdw_mmio_info()
3069 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0, in init_bdw_mmio_info()
3072 #define RING_REG(base) _MMIO((base) + 0xd0) in init_bdw_mmio_info()
3073 MMIO_RING_F(RING_REG, 4, F_RO, 0, in init_bdw_mmio_info()
3078 #define RING_REG(base) _MMIO((base) + 0x230) in init_bdw_mmio_info()
3079 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); in init_bdw_mmio_info()
3082 #define RING_REG(base) _MMIO((base) + 0x234) in init_bdw_mmio_info()
3083 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, in init_bdw_mmio_info()
3087 #define RING_REG(base) _MMIO((base) + 0x244) in init_bdw_mmio_info()
3091 #define RING_REG(base) _MMIO((base) + 0x370) in init_bdw_mmio_info()
3092 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); in init_bdw_mmio_info()
3095 #define RING_REG(base) _MMIO((base) + 0x3a0) in init_bdw_mmio_info()
3102 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS); in init_bdw_mmio_info()
3105 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS); in init_bdw_mmio_info()
3114 #define RING_REG(base) _MMIO((base) + 0x270) in init_bdw_mmio_info()
3115 MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); in init_bdw_mmio_info()
3129 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS); in init_bdw_mmio_info()
3130 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS); in init_bdw_mmio_info()
3131 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS); in init_bdw_mmio_info()
3139 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS); in init_bdw_mmio_info()
3146 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3147 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3149 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3150 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3151 MMIO_D(_MMIO(0xb110), D_BDW); in init_bdw_mmio_info()
3154 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0, in init_bdw_mmio_info()
3157 MMIO_D(_MMIO(0x44484), D_BDW_PLUS); in init_bdw_mmio_info()
3158 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS); in init_bdw_mmio_info()
3160 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3163 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3165 MMIO_D(_MMIO(0x110000), D_BDW_PLUS); in init_bdw_mmio_info()
3167 MMIO_D(_MMIO(0x48400), D_BDW_PLUS); in init_bdw_mmio_info()
3169 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS); in init_bdw_mmio_info()
3170 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS); in init_bdw_mmio_info()
3172 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3173 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3175 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3177 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3179 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3180 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3181 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3182 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3183 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3184 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3185 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3186 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3187 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3188 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
3189 return 0; in init_bdw_mmio_info()
3204 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, in init_skl_mmio_info()
3206 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, in init_skl_mmio_info()
3208 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, in init_skl_mmio_info()
3214 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); in init_skl_mmio_info()
3237 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
3239 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
3241 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
3244 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
3246 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
3248 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
3251 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
3253 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
3255 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
3258 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3263 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3268 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3277 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3278 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3279 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3281 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3282 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3283 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3285 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3286 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3287 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3289 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3290 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3291 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3293 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3297 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3301 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3309 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3314 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3319 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
3356 MMIO_D(_MMIO(0x72380), D_SKL_PLUS); in init_skl_mmio_info()
3357 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS); in init_skl_mmio_info()
3370 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, in init_skl_mmio_info()
3372 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, in init_skl_mmio_info()
3376 MMIO_D(_MMIO(0xd08), D_SKL_PLUS); in init_skl_mmio_info()
3384 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); in init_skl_mmio_info()
3391 MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE, in init_skl_mmio_info()
3394 MMIO_D(_MMIO(0x46430), D_SKL_PLUS); in init_skl_mmio_info()
3396 MMIO_D(_MMIO(0x46520), D_SKL_PLUS); in init_skl_mmio_info()
3398 MMIO_D(_MMIO(0xc403c), D_SKL_PLUS); in init_skl_mmio_info()
3402 MMIO_D(_MMIO(0x65900), D_SKL_PLUS); in init_skl_mmio_info()
3404 MMIO_D(_MMIO(0x4068), D_SKL_PLUS); in init_skl_mmio_info()
3405 MMIO_D(_MMIO(0x67054), D_SKL_PLUS); in init_skl_mmio_info()
3406 MMIO_D(_MMIO(0x6e560), D_SKL_PLUS); in init_skl_mmio_info()
3407 MMIO_D(_MMIO(0x6e554), D_SKL_PLUS); in init_skl_mmio_info()
3408 MMIO_D(_MMIO(0x2b20), D_SKL_PLUS); in init_skl_mmio_info()
3409 MMIO_D(_MMIO(0x65f00), D_SKL_PLUS); in init_skl_mmio_info()
3410 MMIO_D(_MMIO(0x65f08), D_SKL_PLUS); in init_skl_mmio_info()
3411 MMIO_D(_MMIO(0x320f0), D_SKL_PLUS); in init_skl_mmio_info()
3413 MMIO_D(_MMIO(0x70034), D_SKL_PLUS); in init_skl_mmio_info()
3414 MMIO_D(_MMIO(0x71034), D_SKL_PLUS); in init_skl_mmio_info()
3415 MMIO_D(_MMIO(0x72034), D_SKL_PLUS); in init_skl_mmio_info()
3427 MMIO_D(_MMIO(0x44500), D_SKL_PLUS); in init_skl_mmio_info()
3428 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) in init_skl_mmio_info()
3440 return 0; in init_skl_mmio_info()
3448 MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL); in init_bxt_mmio_info()
3458 MMIO_D(_MMIO(0x4194), D_BXT); in init_bxt_mmio_info()
3459 MMIO_D(_MMIO(0x4294), D_BXT); in init_bxt_mmio_info()
3460 MMIO_D(_MMIO(0x4494), D_BXT); in init_bxt_mmio_info()
3471 MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL); in init_bxt_mmio_info()
3524 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT); in init_bxt_mmio_info()
3528 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT); in init_bxt_mmio_info()
3552 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT); in init_bxt_mmio_info()
3556 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT); in init_bxt_mmio_info()
3580 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT); in init_bxt_mmio_info()
3584 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT); in init_bxt_mmio_info()
3613 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL); in init_bxt_mmio_info()
3614 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
3615 0, 0, D_BXT, NULL, NULL); in init_bxt_mmio_info()
3616 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
3617 0, 0, D_BXT, NULL, NULL); in init_bxt_mmio_info()
3618 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
3619 0, 0, D_BXT, NULL, NULL); in init_bxt_mmio_info()
3620 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
3621 0, 0, D_BXT, NULL, NULL); in init_bxt_mmio_info()
3627 return 0; in init_bxt_mmio_info()
3638 for (i = 0; i < num; i++, block++) { in find_mmio_block()
3674 {D_SKL_PLUS, _MMIO(DMC_MMIO_START_RANGE), 0x3000, NULL, NULL},
3675 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
3678 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
3679 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL},
3680 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL},
3737 return 0; in intel_gvt_setup_mmio_info()
3766 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { in intel_gvt_for_each_tracked_mmio()
3771 for (j = 0; j < block->size; j += 4) { in intel_gvt_for_each_tracked_mmio()
3779 return 0; in intel_gvt_for_each_tracked_mmio()
3796 return 0; in intel_vgpu_default_mmio_read()
3813 return 0; in intel_vgpu_default_mmio_write()
3837 return 0; in intel_vgpu_mask_mmio_write()
3905 u32 old_vreg = 0; in intel_vgpu_mmio_reg_rw()
3906 u64 data = 0; in intel_vgpu_mmio_reg_rw()
3916 return 0; in intel_vgpu_mmio_reg_rw()
3949 for (i = 0; i < vgpu_fence_sz(vgpu); i++) in intel_gvt_restore_fence()
3963 return 0; in mmio_pm_restore_handler()