1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/clock/qcom,gcc-msm8960.h>
5#include <dt-bindings/reset/qcom,gcc-msm8960.h>
6#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7#include <dt-bindings/clock/qcom,rpmcc.h>
8#include <dt-bindings/soc/qcom,gsbi.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14	model = "Qualcomm APQ8064";
15	compatible = "qcom,apq8064";
16	interrupt-parent = <&intc>;
17
18	reserved-memory {
19		#address-cells = <1>;
20		#size-cells = <1>;
21		ranges;
22
23		smem_region: smem@80000000 {
24			reg = <0x80000000 0x200000>;
25			no-map;
26		};
27
28		wcnss_mem: wcnss@8f000000 {
29			reg = <0x8f000000 0x700000>;
30			no-map;
31		};
32	};
33
34	cpus {
35		#address-cells = <1>;
36		#size-cells = <0>;
37
38		CPU0: cpu@0 {
39			compatible = "qcom,krait";
40			enable-method = "qcom,kpss-acc-v1";
41			device_type = "cpu";
42			reg = <0>;
43			next-level-cache = <&L2>;
44			qcom,acc = <&acc0>;
45			qcom,saw = <&saw0>;
46			cpu-idle-states = <&CPU_SPC>;
47		};
48
49		CPU1: cpu@1 {
50			compatible = "qcom,krait";
51			enable-method = "qcom,kpss-acc-v1";
52			device_type = "cpu";
53			reg = <1>;
54			next-level-cache = <&L2>;
55			qcom,acc = <&acc1>;
56			qcom,saw = <&saw1>;
57			cpu-idle-states = <&CPU_SPC>;
58		};
59
60		CPU2: cpu@2 {
61			compatible = "qcom,krait";
62			enable-method = "qcom,kpss-acc-v1";
63			device_type = "cpu";
64			reg = <2>;
65			next-level-cache = <&L2>;
66			qcom,acc = <&acc2>;
67			qcom,saw = <&saw2>;
68			cpu-idle-states = <&CPU_SPC>;
69		};
70
71		CPU3: cpu@3 {
72			compatible = "qcom,krait";
73			enable-method = "qcom,kpss-acc-v1";
74			device_type = "cpu";
75			reg = <3>;
76			next-level-cache = <&L2>;
77			qcom,acc = <&acc3>;
78			qcom,saw = <&saw3>;
79			cpu-idle-states = <&CPU_SPC>;
80		};
81
82		L2: l2-cache {
83			compatible = "cache";
84			cache-level = <2>;
85		};
86
87		idle-states {
88			CPU_SPC: spc {
89				compatible = "qcom,idle-state-spc",
90						"arm,idle-state";
91				entry-latency-us = <400>;
92				exit-latency-us = <900>;
93				min-residency-us = <3000>;
94			};
95		};
96	};
97
98	memory {
99		device_type = "memory";
100		reg = <0x0 0x0>;
101	};
102
103	thermal-zones {
104		cpu-thermal0 {
105			polling-delay-passive = <250>;
106			polling-delay = <1000>;
107
108			thermal-sensors = <&gcc 7>;
109			coefficients = <1199 0>;
110
111			trips {
112				cpu_alert0: trip0 {
113					temperature = <75000>;
114					hysteresis = <2000>;
115					type = "passive";
116				};
117				cpu_crit0: trip1 {
118					temperature = <110000>;
119					hysteresis = <2000>;
120					type = "critical";
121				};
122			};
123		};
124
125		cpu-thermal1 {
126			polling-delay-passive = <250>;
127			polling-delay = <1000>;
128
129			thermal-sensors = <&gcc 8>;
130			coefficients = <1132 0>;
131
132			trips {
133				cpu_alert1: trip0 {
134					temperature = <75000>;
135					hysteresis = <2000>;
136					type = "passive";
137				};
138				cpu_crit1: trip1 {
139					temperature = <110000>;
140					hysteresis = <2000>;
141					type = "critical";
142				};
143			};
144		};
145
146		cpu-thermal2 {
147			polling-delay-passive = <250>;
148			polling-delay = <1000>;
149
150			thermal-sensors = <&gcc 9>;
151			coefficients = <1199 0>;
152
153			trips {
154				cpu_alert2: trip0 {
155					temperature = <75000>;
156					hysteresis = <2000>;
157					type = "passive";
158				};
159				cpu_crit2: trip1 {
160					temperature = <110000>;
161					hysteresis = <2000>;
162					type = "critical";
163				};
164			};
165		};
166
167		cpu-thermal3 {
168			polling-delay-passive = <250>;
169			polling-delay = <1000>;
170
171			thermal-sensors = <&gcc 10>;
172			coefficients = <1132 0>;
173
174			trips {
175				cpu_alert3: trip0 {
176					temperature = <75000>;
177					hysteresis = <2000>;
178					type = "passive";
179				};
180				cpu_crit3: trip1 {
181					temperature = <110000>;
182					hysteresis = <2000>;
183					type = "critical";
184				};
185			};
186		};
187	};
188
189	cpu-pmu {
190		compatible = "qcom,krait-pmu";
191		interrupts = <1 10 0x304>;
192	};
193
194	clocks {
195		cxo_board: cxo_board {
196			compatible = "fixed-clock";
197			#clock-cells = <0>;
198			clock-frequency = <19200000>;
199		};
200
201		pxo_board: pxo_board {
202			compatible = "fixed-clock";
203			#clock-cells = <0>;
204			clock-frequency = <27000000>;
205		};
206
207		sleep_clk: sleep_clk {
208			compatible = "fixed-clock";
209			#clock-cells = <0>;
210			clock-frequency = <32768>;
211		};
212	};
213
214	sfpb_mutex: hwmutex {
215		compatible = "qcom,sfpb-mutex";
216		syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
217		#hwlock-cells = <1>;
218	};
219
220	smem {
221		compatible = "qcom,smem";
222		memory-region = <&smem_region>;
223
224		hwlocks = <&sfpb_mutex 3>;
225	};
226
227	smd {
228		compatible = "qcom,smd";
229
230		modem@0 {
231			interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
232
233			qcom,ipc = <&l2cc 8 3>;
234			qcom,smd-edge = <0>;
235
236			status = "disabled";
237		};
238
239		q6@1 {
240			interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
241
242			qcom,ipc = <&l2cc 8 15>;
243			qcom,smd-edge = <1>;
244
245			status = "disabled";
246		};
247
248		dsps@3 {
249			interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
250
251			qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
252			qcom,smd-edge = <3>;
253
254			status = "disabled";
255		};
256
257		riva@6 {
258			interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
259
260			qcom,ipc = <&l2cc 8 25>;
261			qcom,smd-edge = <6>;
262
263			status = "disabled";
264		};
265	};
266
267	smsm {
268		compatible = "qcom,smsm";
269
270		#address-cells = <1>;
271		#size-cells = <0>;
272
273		qcom,ipc-1 = <&l2cc 8 4>;
274		qcom,ipc-2 = <&l2cc 8 14>;
275		qcom,ipc-3 = <&l2cc 8 23>;
276		qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
277
278		apps_smsm: apps@0 {
279			reg = <0>;
280			#qcom,smem-state-cells = <1>;
281		};
282
283		modem_smsm: modem@1 {
284			reg = <1>;
285			interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
286
287			interrupt-controller;
288			#interrupt-cells = <2>;
289		};
290
291		q6_smsm: q6@2 {
292			reg = <2>;
293			interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
294
295			interrupt-controller;
296			#interrupt-cells = <2>;
297		};
298
299		wcnss_smsm: wcnss@3 {
300			reg = <3>;
301			interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
302
303			interrupt-controller;
304			#interrupt-cells = <2>;
305		};
306
307		dsps_smsm: dsps@4 {
308			reg = <4>;
309			interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
310
311			interrupt-controller;
312			#interrupt-cells = <2>;
313		};
314	};
315
316	firmware {
317		scm {
318			compatible = "qcom,scm-apq8064";
319
320			clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
321			clock-names = "core";
322		};
323	};
324
325
326	/*
327	 * These channels from the ADC are simply hardware monitors.
328	 * That is why the ADC is referred to as "HKADC" - HouseKeeping
329	 * ADC.
330	 */
331	iio-hwmon {
332		compatible = "iio-hwmon";
333		io-channels = <&xoadc 0x00 0x01>, /* Battery */
334			    <&xoadc 0x00 0x02>, /* DC in (charger) */
335			    <&xoadc 0x00 0x04>, /* VPH the main system voltage */
336			    <&xoadc 0x00 0x0b>, /* Die temperature */
337			    <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
338			    <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
339			    <&xoadc 0x00 0x0e>; /* Charger temperature */
340	};
341
342	soc: soc {
343		#address-cells = <1>;
344		#size-cells = <1>;
345		ranges;
346		compatible = "simple-bus";
347
348		tlmm_pinmux: pinctrl@800000 {
349			compatible = "qcom,apq8064-pinctrl";
350			reg = <0x800000 0x4000>;
351
352			gpio-controller;
353			gpio-ranges = <&tlmm_pinmux 0 0 90>;
354			#gpio-cells = <2>;
355			interrupt-controller;
356			#interrupt-cells = <2>;
357			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
358
359			pinctrl-names = "default";
360			pinctrl-0 = <&ps_hold>;
361		};
362
363		sfpb_wrapper_mutex: syscon@1200000 {
364			compatible = "syscon";
365			reg = <0x01200000 0x8000>;
366		};
367
368		intc: interrupt-controller@2000000 {
369			compatible = "qcom,msm-qgic2";
370			interrupt-controller;
371			#interrupt-cells = <3>;
372			reg = <0x02000000 0x1000>,
373			      <0x02002000 0x1000>;
374		};
375
376		timer@200a000 {
377			compatible = "qcom,kpss-timer",
378				     "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
379			interrupts = <1 1 0x301>,
380				     <1 2 0x301>,
381				     <1 3 0x301>;
382			reg = <0x0200a000 0x100>;
383			clock-frequency = <27000000>,
384					  <32768>;
385			cpu-offset = <0x80000>;
386		};
387
388		acc0: clock-controller@2088000 {
389			compatible = "qcom,kpss-acc-v1";
390			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
391		};
392
393		acc1: clock-controller@2098000 {
394			compatible = "qcom,kpss-acc-v1";
395			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
396		};
397
398		acc2: clock-controller@20a8000 {
399			compatible = "qcom,kpss-acc-v1";
400			reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
401		};
402
403		acc3: clock-controller@20b8000 {
404			compatible = "qcom,kpss-acc-v1";
405			reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
406		};
407
408		saw0: power-controller@2089000 {
409			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
410			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
411			regulator;
412		};
413
414		saw1: power-controller@2099000 {
415			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
416			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
417			regulator;
418		};
419
420		saw2: power-controller@20a9000 {
421			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
422			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
423			regulator;
424		};
425
426		saw3: power-controller@20b9000 {
427			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
428			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
429			regulator;
430		};
431
432		sps_sic_non_secure: sps-sic-non-secure@12100000 {
433			compatible	= "syscon";
434			reg		= <0x12100000 0x10000>;
435		};
436
437		gsbi1: gsbi@12440000 {
438			status = "disabled";
439			compatible = "qcom,gsbi-v1.0.0";
440			cell-index = <1>;
441			reg = <0x12440000 0x100>;
442			clocks = <&gcc GSBI1_H_CLK>;
443			clock-names = "iface";
444			#address-cells = <1>;
445			#size-cells = <1>;
446			ranges;
447
448			syscon-tcsr = <&tcsr>;
449
450			gsbi1_serial: serial@12450000 {
451				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
452				reg = <0x12450000 0x100>,
453				      <0x12400000 0x03>;
454				interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
455				clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
456				clock-names = "core", "iface";
457				status = "disabled";
458			};
459
460			gsbi1_i2c: i2c@12460000 {
461				compatible = "qcom,i2c-qup-v1.1.1";
462				pinctrl-0 = <&i2c1_pins>;
463				pinctrl-1 = <&i2c1_pins_sleep>;
464				pinctrl-names = "default", "sleep";
465				reg = <0x12460000 0x1000>;
466				interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
467				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
468				clock-names = "core", "iface";
469				#address-cells = <1>;
470				#size-cells = <0>;
471				status = "disabled";
472			};
473
474		};
475
476		gsbi2: gsbi@12480000 {
477			status = "disabled";
478			compatible = "qcom,gsbi-v1.0.0";
479			cell-index = <2>;
480			reg = <0x12480000 0x100>;
481			clocks = <&gcc GSBI2_H_CLK>;
482			clock-names = "iface";
483			#address-cells = <1>;
484			#size-cells = <1>;
485			ranges;
486
487			syscon-tcsr = <&tcsr>;
488
489			gsbi2_i2c: i2c@124a0000 {
490				compatible = "qcom,i2c-qup-v1.1.1";
491				reg = <0x124a0000 0x1000>;
492				pinctrl-0 = <&i2c2_pins>;
493				pinctrl-1 = <&i2c2_pins_sleep>;
494				pinctrl-names = "default", "sleep";
495				interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
496				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
497				clock-names = "core", "iface";
498				#address-cells = <1>;
499				#size-cells = <0>;
500				status = "disabled";
501			};
502		};
503
504		gsbi3: gsbi@16200000 {
505			status = "disabled";
506			compatible = "qcom,gsbi-v1.0.0";
507			cell-index = <3>;
508			reg = <0x16200000 0x100>;
509			clocks = <&gcc GSBI3_H_CLK>;
510			clock-names = "iface";
511			#address-cells = <1>;
512			#size-cells = <1>;
513			ranges;
514			gsbi3_i2c: i2c@16280000 {
515				compatible = "qcom,i2c-qup-v1.1.1";
516				pinctrl-0 = <&i2c3_pins>;
517				pinctrl-1 = <&i2c3_pins_sleep>;
518				pinctrl-names = "default", "sleep";
519				reg = <0x16280000 0x1000>;
520				interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
521				clocks = <&gcc GSBI3_QUP_CLK>,
522					 <&gcc GSBI3_H_CLK>;
523				clock-names = "core", "iface";
524				#address-cells = <1>;
525				#size-cells = <0>;
526				status = "disabled";
527			};
528		};
529
530		gsbi4: gsbi@16300000 {
531			status = "disabled";
532			compatible = "qcom,gsbi-v1.0.0";
533			cell-index = <4>;
534			reg = <0x16300000 0x03>;
535			clocks = <&gcc GSBI4_H_CLK>;
536			clock-names = "iface";
537			#address-cells = <1>;
538			#size-cells = <1>;
539			ranges;
540
541			gsbi4_i2c: i2c@16380000 {
542				compatible = "qcom,i2c-qup-v1.1.1";
543				pinctrl-0 = <&i2c4_pins>;
544				pinctrl-1 = <&i2c4_pins_sleep>;
545				pinctrl-names = "default", "sleep";
546				reg = <0x16380000 0x1000>;
547				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
548				clocks = <&gcc GSBI4_QUP_CLK>,
549					 <&gcc GSBI4_H_CLK>;
550				clock-names = "core", "iface";
551				status = "disabled";
552			};
553		};
554
555		gsbi5: gsbi@1a200000 {
556			status = "disabled";
557			compatible = "qcom,gsbi-v1.0.0";
558			cell-index = <5>;
559			reg = <0x1a200000 0x03>;
560			clocks = <&gcc GSBI5_H_CLK>;
561			clock-names = "iface";
562			#address-cells = <1>;
563			#size-cells = <1>;
564			ranges;
565
566			gsbi5_serial: serial@1a240000 {
567				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
568				reg = <0x1a240000 0x100>,
569				      <0x1a200000 0x03>;
570				interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
571				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
572				clock-names = "core", "iface";
573				status = "disabled";
574			};
575
576			gsbi5_spi: spi@1a280000 {
577				compatible = "qcom,spi-qup-v1.1.1";
578				reg = <0x1a280000 0x1000>;
579				interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
580				pinctrl-0 = <&spi5_default>;
581				pinctrl-1 = <&spi5_sleep>;
582				pinctrl-names = "default", "sleep";
583				clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
584				clock-names = "core", "iface";
585				status = "disabled";
586				#address-cells = <1>;
587				#size-cells = <0>;
588			};
589		};
590
591		gsbi6: gsbi@16500000 {
592			status = "disabled";
593			compatible = "qcom,gsbi-v1.0.0";
594			cell-index = <6>;
595			reg = <0x16500000 0x03>;
596			clocks = <&gcc GSBI6_H_CLK>;
597			clock-names = "iface";
598			#address-cells = <1>;
599			#size-cells = <1>;
600			ranges;
601
602			gsbi6_serial: serial@16540000 {
603				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
604				reg = <0x16540000 0x100>,
605				      <0x16500000 0x03>;
606				interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
607				clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
608				clock-names = "core", "iface";
609				status = "disabled";
610			};
611
612			gsbi6_i2c: i2c@16580000 {
613				compatible = "qcom,i2c-qup-v1.1.1";
614				pinctrl-0 = <&i2c6_pins>;
615				pinctrl-1 = <&i2c6_pins_sleep>;
616				pinctrl-names = "default", "sleep";
617				reg = <0x16580000 0x1000>;
618				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
619				clocks = <&gcc GSBI6_QUP_CLK>,
620					 <&gcc GSBI6_H_CLK>;
621				clock-names = "core", "iface";
622				status = "disabled";
623			};
624		};
625
626		gsbi7: gsbi@16600000 {
627			status = "disabled";
628			compatible = "qcom,gsbi-v1.0.0";
629			cell-index = <7>;
630			reg = <0x16600000 0x100>;
631			clocks = <&gcc GSBI7_H_CLK>;
632			clock-names = "iface";
633			#address-cells = <1>;
634			#size-cells = <1>;
635			ranges;
636			syscon-tcsr = <&tcsr>;
637
638			gsbi7_serial: serial@16640000 {
639				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
640				reg = <0x16640000 0x1000>,
641				      <0x16600000 0x1000>;
642				interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
643				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
644				clock-names = "core", "iface";
645				status = "disabled";
646			};
647
648			gsbi7_i2c: i2c@16680000 {
649				compatible = "qcom,i2c-qup-v1.1.1";
650				pinctrl-0 = <&i2c7_pins>;
651				pinctrl-1 = <&i2c7_pins_sleep>;
652				pinctrl-names = "default", "sleep";
653				reg = <0x16680000 0x1000>;
654				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
655				clocks = <&gcc GSBI7_QUP_CLK>,
656					 <&gcc GSBI7_H_CLK>;
657				clock-names = "core", "iface";
658				status = "disabled";
659			};
660		};
661
662		rng@1a500000 {
663			compatible = "qcom,prng";
664			reg = <0x1a500000 0x200>;
665			clocks = <&gcc PRNG_CLK>;
666			clock-names = "core";
667		};
668
669		ssbi@c00000 {
670			compatible = "qcom,ssbi";
671			reg = <0x00c00000 0x1000>;
672			qcom,controller-type = "pmic-arbiter";
673
674			pm8821: pmic@1 {
675				compatible = "qcom,pm8821";
676				interrupt-parent = <&tlmm_pinmux>;
677				interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
678				#interrupt-cells = <2>;
679				interrupt-controller;
680				#address-cells = <1>;
681				#size-cells = <0>;
682
683				pm8821_mpps: mpps@50 {
684					compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
685					reg = <0x50>;
686					interrupts = <24 IRQ_TYPE_NONE>,
687						     <25 IRQ_TYPE_NONE>,
688						     <26 IRQ_TYPE_NONE>,
689						     <27 IRQ_TYPE_NONE>;
690					gpio-controller;
691					#gpio-cells = <2>;
692				};
693			};
694		};
695
696		qcom,ssbi@500000 {
697			compatible = "qcom,ssbi";
698			reg = <0x00500000 0x1000>;
699			qcom,controller-type = "pmic-arbiter";
700
701			pmicintc: pmic@0 {
702				compatible = "qcom,pm8921";
703				interrupt-parent = <&tlmm_pinmux>;
704				interrupts = <74 8>;
705				#interrupt-cells = <2>;
706				interrupt-controller;
707				#address-cells = <1>;
708				#size-cells = <0>;
709
710				pm8921_gpio: gpio@150 {
711
712					compatible = "qcom,pm8921-gpio",
713						     "qcom,ssbi-gpio";
714					reg = <0x150>;
715					interrupt-controller;
716					#interrupt-cells = <2>;
717					gpio-controller;
718					gpio-ranges = <&pm8921_gpio 0 0 44>;
719					#gpio-cells = <2>;
720
721				};
722
723				pm8921_mpps: mpps@50 {
724					compatible = "qcom,pm8921-mpp",
725						     "qcom,ssbi-mpp";
726					reg = <0x50>;
727					gpio-controller;
728					#gpio-cells = <2>;
729					interrupts =
730					<128 IRQ_TYPE_NONE>,
731					<129 IRQ_TYPE_NONE>,
732					<130 IRQ_TYPE_NONE>,
733					<131 IRQ_TYPE_NONE>,
734					<132 IRQ_TYPE_NONE>,
735					<133 IRQ_TYPE_NONE>,
736					<134 IRQ_TYPE_NONE>,
737					<135 IRQ_TYPE_NONE>,
738					<136 IRQ_TYPE_NONE>,
739					<137 IRQ_TYPE_NONE>,
740					<138 IRQ_TYPE_NONE>,
741					<139 IRQ_TYPE_NONE>;
742				};
743
744				rtc@11d {
745					compatible = "qcom,pm8921-rtc";
746					interrupt-parent = <&pmicintc>;
747					interrupts = <39 1>;
748					reg = <0x11d>;
749					allow-set-time;
750				};
751
752				pwrkey@1c {
753					compatible = "qcom,pm8921-pwrkey";
754					reg = <0x1c>;
755					interrupt-parent = <&pmicintc>;
756					interrupts = <50 1>, <51 1>;
757					debounce = <15625>;
758					pull-up;
759				};
760
761				xoadc: xoadc@197 {
762					compatible = "qcom,pm8921-adc";
763					reg = <197>;
764					interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
765					#address-cells = <2>;
766					#size-cells = <0>;
767					#io-channel-cells = <2>;
768
769					vcoin: adc-channel@0 {
770						reg = <0x00 0x00>;
771					};
772					vbat: adc-channel@1 {
773						reg = <0x00 0x01>;
774					};
775					dcin: adc-channel@2 {
776						reg = <0x00 0x02>;
777					};
778					vph_pwr: adc-channel@4 {
779						reg = <0x00 0x04>;
780					};
781					batt_therm: adc-channel@8 {
782						reg = <0x00 0x08>;
783					};
784					batt_id: adc-channel@9 {
785						reg = <0x00 0x09>;
786					};
787					usb_vbus: adc-channel@a {
788						reg = <0x00 0x0a>;
789					};
790					die_temp: adc-channel@b {
791						reg = <0x00 0x0b>;
792					};
793					ref_625mv: adc-channel@c {
794						reg = <0x00 0x0c>;
795					};
796					ref_1250mv: adc-channel@d {
797						reg = <0x00 0x0d>;
798					};
799					chg_temp: adc-channel@e {
800						reg = <0x00 0x0e>;
801					};
802					ref_muxoff: adc-channel@f {
803						reg = <0x00 0x0f>;
804					};
805				};
806			};
807		};
808
809		qfprom: qfprom@700000 {
810			compatible	= "qcom,qfprom";
811			reg		= <0x00700000 0x1000>;
812			#address-cells	= <1>;
813			#size-cells	= <1>;
814			ranges;
815			tsens_calib: calib {
816				reg = <0x404 0x10>;
817			};
818			tsens_backup: backup_calib {
819				reg = <0x414 0x10>;
820			};
821		};
822
823		gcc: clock-controller@900000 {
824			compatible = "qcom,gcc-apq8064";
825			reg = <0x00900000 0x4000>;
826			nvmem-cells = <&tsens_calib>, <&tsens_backup>;
827			nvmem-cell-names = "calib", "calib_backup";
828			#clock-cells = <1>;
829			#reset-cells = <1>;
830			#thermal-sensor-cells = <1>;
831		};
832
833		lcc: clock-controller@28000000 {
834			compatible = "qcom,lcc-apq8064";
835			reg = <0x28000000 0x1000>;
836			#clock-cells = <1>;
837			#reset-cells = <1>;
838		};
839
840		mmcc: clock-controller@4000000 {
841			compatible = "qcom,mmcc-apq8064";
842			reg = <0x4000000 0x1000>;
843			#clock-cells = <1>;
844			#reset-cells = <1>;
845		};
846
847		l2cc: clock-controller@2011000 {
848			compatible	= "syscon";
849			reg		= <0x2011000 0x1000>;
850		};
851
852		rpm@108000 {
853			compatible	= "qcom,rpm-apq8064";
854			reg		= <0x108000 0x1000>;
855			qcom,ipc	= <&l2cc 0x8 2>;
856
857			interrupts	= <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
858					  <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
859					  <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
860			interrupt-names	= "ack", "err", "wakeup";
861
862			rpmcc: clock-controller {
863				compatible	= "qcom,rpmcc-apq8064", "qcom,rpmcc";
864				#clock-cells = <1>;
865			};
866
867			regulators {
868				compatible = "qcom,rpm-pm8921-regulators";
869
870				pm8921_s1: s1 {};
871				pm8921_s2: s2 {};
872				pm8921_s3: s3 {};
873				pm8921_s4: s4 {};
874				pm8921_s7: s7 {};
875				pm8921_s8: s8 {};
876
877				pm8921_l1: l1 {};
878				pm8921_l2: l2 {};
879				pm8921_l3: l3 {};
880				pm8921_l4: l4 {};
881				pm8921_l5: l5 {};
882				pm8921_l6: l6 {};
883				pm8921_l7: l7 {};
884				pm8921_l8: l8 {};
885				pm8921_l9: l9 {};
886				pm8921_l10: l10 {};
887				pm8921_l11: l11 {};
888				pm8921_l12: l12 {};
889				pm8921_l14: l14 {};
890				pm8921_l15: l15 {};
891				pm8921_l16: l16 {};
892				pm8921_l17: l17 {};
893				pm8921_l18: l18 {};
894				pm8921_l21: l21 {};
895				pm8921_l22: l22 {};
896				pm8921_l23: l23 {};
897				pm8921_l24: l24 {};
898				pm8921_l25: l25 {};
899				pm8921_l26: l26 {};
900				pm8921_l27: l27 {};
901				pm8921_l28: l28 {};
902				pm8921_l29: l29 {};
903
904				pm8921_lvs1: lvs1 {};
905				pm8921_lvs2: lvs2 {};
906				pm8921_lvs3: lvs3 {};
907				pm8921_lvs4: lvs4 {};
908				pm8921_lvs5: lvs5 {};
909				pm8921_lvs6: lvs6 {};
910				pm8921_lvs7: lvs7 {};
911
912				pm8921_usb_switch: usb-switch {};
913
914				pm8921_hdmi_switch: hdmi-switch {
915					bias-pull-down;
916				};
917
918				pm8921_ncp: ncp {};
919			};
920		};
921
922		usb1: usb@12500000 {
923			compatible = "qcom,ci-hdrc";
924			reg = <0x12500000 0x200>,
925			      <0x12500200 0x200>;
926			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
927			clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
928			clock-names = "core", "iface";
929			assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
930			assigned-clock-rates = <60000000>;
931			resets = <&gcc USB_HS1_RESET>;
932			reset-names = "core";
933			phy_type = "ulpi";
934			ahb-burst-config = <0>;
935			phys = <&usb_hs1_phy>;
936			phy-names = "usb-phy";
937			status = "disabled";
938			#reset-cells = <1>;
939
940			ulpi {
941				usb_hs1_phy: phy {
942					compatible = "qcom,usb-hs-phy-apq8064",
943						     "qcom,usb-hs-phy";
944					clocks = <&sleep_clk>, <&cxo_board>;
945					clock-names = "sleep", "ref";
946					resets = <&usb1 0>;
947					reset-names = "por";
948					#phy-cells = <0>;
949				};
950			};
951		};
952
953		usb3: usb@12520000 {
954			compatible = "qcom,ci-hdrc";
955			reg = <0x12520000 0x200>,
956			      <0x12520200 0x200>;
957			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
958			clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
959			clock-names = "core", "iface";
960			assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
961			assigned-clock-rates = <60000000>;
962			resets = <&gcc USB_HS3_RESET>;
963			reset-names = "core";
964			phy_type = "ulpi";
965			ahb-burst-config = <0>;
966			phys = <&usb_hs3_phy>;
967			phy-names = "usb-phy";
968			status = "disabled";
969			#reset-cells = <1>;
970
971			ulpi {
972				usb_hs3_phy: phy {
973					compatible = "qcom,usb-hs-phy-apq8064",
974						     "qcom,usb-hs-phy";
975					#phy-cells = <0>;
976					clocks = <&sleep_clk>, <&cxo_board>;
977					clock-names = "sleep", "ref";
978					resets = <&usb3 0>;
979					reset-names = "por";
980				};
981			};
982		};
983
984		usb4: usb@12530000 {
985			compatible = "qcom,ci-hdrc";
986			reg = <0x12530000 0x200>,
987			      <0x12530200 0x200>;
988			interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
989			clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
990			clock-names = "core", "iface";
991			assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
992			assigned-clock-rates = <60000000>;
993			resets = <&gcc USB_HS4_RESET>;
994			reset-names = "core";
995			phy_type = "ulpi";
996			ahb-burst-config = <0>;
997			phys = <&usb_hs4_phy>;
998			phy-names = "usb-phy";
999			status = "disabled";
1000			#reset-cells = <1>;
1001
1002			ulpi {
1003				usb_hs4_phy: phy {
1004					compatible = "qcom,usb-hs-phy-apq8064",
1005						     "qcom,usb-hs-phy";
1006					#phy-cells = <0>;
1007					clocks = <&sleep_clk>, <&cxo_board>;
1008					clock-names = "sleep", "ref";
1009					resets = <&usb4 0>;
1010					reset-names = "por";
1011				};
1012			};
1013		};
1014
1015		sata_phy0: phy@1b400000 {
1016			compatible	= "qcom,apq8064-sata-phy";
1017			status		= "disabled";
1018			reg		= <0x1b400000 0x200>;
1019			reg-names	= "phy_mem";
1020			clocks		= <&gcc SATA_PHY_CFG_CLK>;
1021			clock-names	= "cfg";
1022			#phy-cells	= <0>;
1023		};
1024
1025		sata0: sata@29000000 {
1026			compatible		= "qcom,apq8064-ahci", "generic-ahci";
1027			status			= "disabled";
1028			reg			= <0x29000000 0x180>;
1029			interrupts		= <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1030
1031			clocks			= <&gcc SFAB_SATA_S_H_CLK>,
1032						<&gcc SATA_H_CLK>,
1033						<&gcc SATA_A_CLK>,
1034						<&gcc SATA_RXOOB_CLK>,
1035						<&gcc SATA_PMALIVE_CLK>;
1036			clock-names		= "slave_iface",
1037						"iface",
1038						"bus",
1039						"rxoob",
1040						"core_pmalive";
1041
1042			assigned-clocks		= <&gcc SATA_RXOOB_CLK>,
1043						<&gcc SATA_PMALIVE_CLK>;
1044			assigned-clock-rates	= <100000000>, <100000000>;
1045
1046			phys			= <&sata_phy0>;
1047			phy-names		= "sata-phy";
1048			ports-implemented	= <0x1>;
1049		};
1050
1051		/* Temporary fixed regulator */
1052		sdcc1bam:dma@12402000{
1053			compatible = "qcom,bam-v1.3.0";
1054			reg = <0x12402000 0x8000>;
1055			interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1056			clocks = <&gcc SDC1_H_CLK>;
1057			clock-names = "bam_clk";
1058			#dma-cells = <1>;
1059			qcom,ee = <0>;
1060		};
1061
1062		sdcc3bam:dma@12182000{
1063			compatible = "qcom,bam-v1.3.0";
1064			reg = <0x12182000 0x8000>;
1065			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
1066			clocks = <&gcc SDC3_H_CLK>;
1067			clock-names = "bam_clk";
1068			#dma-cells = <1>;
1069			qcom,ee = <0>;
1070		};
1071
1072		sdcc4bam:dma@121c2000{
1073			compatible = "qcom,bam-v1.3.0";
1074			reg = <0x121c2000 0x8000>;
1075			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
1076			clocks = <&gcc SDC4_H_CLK>;
1077			clock-names = "bam_clk";
1078			#dma-cells = <1>;
1079			qcom,ee = <0>;
1080		};
1081
1082		amba {
1083			compatible = "simple-bus";
1084			#address-cells = <1>;
1085			#size-cells = <1>;
1086			ranges;
1087			sdcc1: sdcc@12400000 {
1088				status		= "disabled";
1089				compatible	= "arm,pl18x", "arm,primecell";
1090				pinctrl-names	= "default";
1091				pinctrl-0	= <&sdcc1_pins>;
1092				arm,primecell-periphid = <0x00051180>;
1093				reg		= <0x12400000 0x2000>;
1094				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1095				interrupt-names	= "cmd_irq";
1096				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1097				clock-names	= "mclk", "apb_pclk";
1098				bus-width	= <8>;
1099				max-frequency	= <96000000>;
1100				non-removable;
1101				cap-sd-highspeed;
1102				cap-mmc-highspeed;
1103				dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1104				dma-names = "tx", "rx";
1105			};
1106
1107			sdcc3: sdcc@12180000 {
1108				compatible	= "arm,pl18x", "arm,primecell";
1109				arm,primecell-periphid = <0x00051180>;
1110				status		= "disabled";
1111				reg		= <0x12180000 0x2000>;
1112				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1113				interrupt-names	= "cmd_irq";
1114				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1115				clock-names	= "mclk", "apb_pclk";
1116				bus-width	= <4>;
1117				cap-sd-highspeed;
1118				cap-mmc-highspeed;
1119				max-frequency	= <192000000>;
1120				no-1-8-v;
1121				dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1122				dma-names = "tx", "rx";
1123			};
1124
1125			sdcc4: sdcc@121c0000 {
1126				compatible	= "arm,pl18x", "arm,primecell";
1127				arm,primecell-periphid = <0x00051180>;
1128				status		= "disabled";
1129				reg		= <0x121c0000 0x2000>;
1130				interrupts	= <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1131				interrupt-names	= "cmd_irq";
1132				clocks		= <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1133				clock-names	= "mclk", "apb_pclk";
1134				bus-width	= <4>;
1135				cap-sd-highspeed;
1136				cap-mmc-highspeed;
1137				max-frequency	= <48000000>;
1138				dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1139				dma-names = "tx", "rx";
1140				pinctrl-names = "default";
1141				pinctrl-0 = <&sdc4_gpios>;
1142			};
1143		};
1144
1145		tcsr: syscon@1a400000 {
1146			compatible = "qcom,tcsr-apq8064", "syscon";
1147			reg = <0x1a400000 0x100>;
1148		};
1149
1150		gpu: adreno-3xx@4300000 {
1151			compatible = "qcom,adreno-320.2", "qcom,adreno";
1152			reg = <0x04300000 0x20000>;
1153			reg-names = "kgsl_3d0_reg_memory";
1154			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1155			interrupt-names = "kgsl_3d0_irq";
1156			clock-names =
1157			    "core",
1158			    "iface",
1159			    "mem",
1160			    "mem_iface";
1161			clocks =
1162			    <&mmcc GFX3D_CLK>,
1163			    <&mmcc GFX3D_AHB_CLK>,
1164			    <&mmcc GFX3D_AXI_CLK>,
1165			    <&mmcc MMSS_IMEM_AHB_CLK>;
1166
1167			iommus = <&gfx3d 0
1168				  &gfx3d 1
1169				  &gfx3d 2
1170				  &gfx3d 3
1171				  &gfx3d 4
1172				  &gfx3d 5
1173				  &gfx3d 6
1174				  &gfx3d 7
1175				  &gfx3d 8
1176				  &gfx3d 9
1177				  &gfx3d 10
1178				  &gfx3d 11
1179				  &gfx3d 12
1180				  &gfx3d 13
1181				  &gfx3d 14
1182				  &gfx3d 15
1183				  &gfx3d 16
1184				  &gfx3d 17
1185				  &gfx3d 18
1186				  &gfx3d 19
1187				  &gfx3d 20
1188				  &gfx3d 21
1189				  &gfx3d 22
1190				  &gfx3d 23
1191				  &gfx3d 24
1192				  &gfx3d 25
1193				  &gfx3d 26
1194				  &gfx3d 27
1195				  &gfx3d 28
1196				  &gfx3d 29
1197				  &gfx3d 30
1198				  &gfx3d 31
1199				  &gfx3d1 0
1200				  &gfx3d1 1
1201				  &gfx3d1 2
1202				  &gfx3d1 3
1203				  &gfx3d1 4
1204				  &gfx3d1 5
1205				  &gfx3d1 6
1206				  &gfx3d1 7
1207				  &gfx3d1 8
1208				  &gfx3d1 9
1209				  &gfx3d1 10
1210				  &gfx3d1 11
1211				  &gfx3d1 12
1212				  &gfx3d1 13
1213				  &gfx3d1 14
1214				  &gfx3d1 15
1215				  &gfx3d1 16
1216				  &gfx3d1 17
1217				  &gfx3d1 18
1218				  &gfx3d1 19
1219				  &gfx3d1 20
1220				  &gfx3d1 21
1221				  &gfx3d1 22
1222				  &gfx3d1 23
1223				  &gfx3d1 24
1224				  &gfx3d1 25
1225				  &gfx3d1 26
1226				  &gfx3d1 27
1227				  &gfx3d1 28
1228				  &gfx3d1 29
1229				  &gfx3d1 30
1230				  &gfx3d1 31>;
1231
1232			qcom,gpu-pwrlevels {
1233				compatible = "qcom,gpu-pwrlevels";
1234				qcom,gpu-pwrlevel@0 {
1235					qcom,gpu-freq = <450000000>;
1236				};
1237				qcom,gpu-pwrlevel@1 {
1238					qcom,gpu-freq = <27000000>;
1239				};
1240			};
1241		};
1242
1243		mmss_sfpb: syscon@5700000 {
1244			compatible = "syscon";
1245			reg = <0x5700000 0x70>;
1246		};
1247
1248		dsi0: mdss_dsi@4700000 {
1249			compatible = "qcom,mdss-dsi-ctrl";
1250			label = "MDSS DSI CTRL->0";
1251			#address-cells = <1>;
1252			#size-cells = <0>;
1253			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1254			reg = <0x04700000 0x200>;
1255			reg-names = "dsi_ctrl";
1256
1257			clocks = <&mmcc DSI_M_AHB_CLK>,
1258				<&mmcc DSI_S_AHB_CLK>,
1259				<&mmcc AMP_AHB_CLK>,
1260				<&mmcc DSI_CLK>,
1261				<&mmcc DSI1_BYTE_CLK>,
1262				<&mmcc DSI_PIXEL_CLK>,
1263				<&mmcc DSI1_ESC_CLK>;
1264			clock-names = "iface", "bus", "core_mmss",
1265					"src", "byte", "pixel",
1266					"core";
1267
1268			assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1269					<&mmcc DSI1_ESC_SRC>,
1270					<&mmcc DSI_SRC>,
1271					<&mmcc DSI_PIXEL_SRC>;
1272			assigned-clock-parents = <&dsi0_phy 0>,
1273						<&dsi0_phy 0>,
1274						<&dsi0_phy 1>,
1275						<&dsi0_phy 1>;
1276			syscon-sfpb = <&mmss_sfpb>;
1277			phys = <&dsi0_phy>;
1278			ports {
1279				#address-cells = <1>;
1280				#size-cells = <0>;
1281
1282				port@0 {
1283					reg = <0>;
1284					dsi0_in: endpoint {
1285					};
1286				};
1287
1288				port@1 {
1289					reg = <1>;
1290					dsi0_out: endpoint {
1291					};
1292				};
1293			};
1294		};
1295
1296
1297		dsi0_phy: dsi-phy@4700200 {
1298			compatible = "qcom,dsi-phy-28nm-8960";
1299			#clock-cells = <1>;
1300			#phy-cells = <0>;
1301
1302			reg = <0x04700200 0x100>,
1303				<0x04700300 0x200>,
1304				<0x04700500 0x5c>;
1305			reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1306			clock-names = "iface_clk", "ref";
1307			clocks = <&mmcc DSI_M_AHB_CLK>,
1308				 <&pxo_board>;
1309		};
1310
1311
1312		mdp_port0: iommu@7500000 {
1313			compatible = "qcom,apq8064-iommu";
1314			#iommu-cells = <1>;
1315			clock-names =
1316			    "smmu_pclk",
1317			    "iommu_clk";
1318			clocks =
1319			    <&mmcc SMMU_AHB_CLK>,
1320			    <&mmcc MDP_AXI_CLK>;
1321			reg = <0x07500000 0x100000>;
1322			interrupts =
1323			    <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1324			    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1325			qcom,ncb = <2>;
1326		};
1327
1328		mdp_port1: iommu@7600000 {
1329			compatible = "qcom,apq8064-iommu";
1330			#iommu-cells = <1>;
1331			clock-names =
1332			    "smmu_pclk",
1333			    "iommu_clk";
1334			clocks =
1335			    <&mmcc SMMU_AHB_CLK>,
1336			    <&mmcc MDP_AXI_CLK>;
1337			reg = <0x07600000 0x100000>;
1338			interrupts =
1339			    <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1340			    <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1341			qcom,ncb = <2>;
1342		};
1343
1344		gfx3d: iommu@7c00000 {
1345			compatible = "qcom,apq8064-iommu";
1346			#iommu-cells = <1>;
1347			clock-names =
1348			    "smmu_pclk",
1349			    "iommu_clk";
1350			clocks =
1351			    <&mmcc SMMU_AHB_CLK>,
1352			    <&mmcc GFX3D_AXI_CLK>;
1353			reg = <0x07c00000 0x100000>;
1354			interrupts =
1355			    <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1356			    <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1357			qcom,ncb = <3>;
1358		};
1359
1360		gfx3d1: iommu@7d00000 {
1361			compatible = "qcom,apq8064-iommu";
1362			#iommu-cells = <1>;
1363			clock-names =
1364			    "smmu_pclk",
1365			    "iommu_clk";
1366			clocks =
1367			    <&mmcc SMMU_AHB_CLK>,
1368			    <&mmcc GFX3D_AXI_CLK>;
1369			reg = <0x07d00000 0x100000>;
1370			interrupts =
1371			    <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1372			    <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1373			qcom,ncb = <3>;
1374		};
1375
1376		pcie: pci@1b500000 {
1377			compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1378			reg = <0x1b500000 0x1000
1379			       0x1b502000 0x80
1380			       0x1b600000 0x100
1381			       0x0ff00000 0x100000>;
1382			reg-names = "dbi", "elbi", "parf", "config";
1383			device_type = "pci";
1384			linux,pci-domain = <0>;
1385			bus-range = <0x00 0xff>;
1386			num-lanes = <1>;
1387			#address-cells = <3>;
1388			#size-cells = <2>;
1389			ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
1390				  0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */
1391			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1392			interrupt-names = "msi";
1393			#interrupt-cells = <1>;
1394			interrupt-map-mask = <0 0 0 0x7>;
1395			interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1396					<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1397					<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1398					<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1399			clocks = <&gcc PCIE_A_CLK>,
1400				 <&gcc PCIE_H_CLK>,
1401				 <&gcc PCIE_PHY_REF_CLK>;
1402			clock-names = "core", "iface", "phy";
1403			resets = <&gcc PCIE_ACLK_RESET>,
1404				 <&gcc PCIE_HCLK_RESET>,
1405				 <&gcc PCIE_POR_RESET>,
1406				 <&gcc PCIE_PCI_RESET>,
1407				 <&gcc PCIE_PHY_RESET>;
1408			reset-names = "axi", "ahb", "por", "pci", "phy";
1409			status = "disabled";
1410		};
1411
1412		hdmi: hdmi-tx@4a00000 {
1413			compatible = "qcom,hdmi-tx-8960";
1414			pinctrl-names = "default";
1415			pinctrl-0 = <&hdmi_pinctrl>;
1416			reg = <0x04a00000 0x2f0>;
1417			reg-names = "core_physical";
1418			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1419			clocks = <&mmcc HDMI_APP_CLK>,
1420				 <&mmcc HDMI_M_AHB_CLK>,
1421				 <&mmcc HDMI_S_AHB_CLK>;
1422			clock-names = "core_clk",
1423				      "master_iface_clk",
1424				      "slave_iface_clk";
1425
1426			phys = <&hdmi_phy>;
1427			phy-names = "hdmi-phy";
1428
1429			ports {
1430				#address-cells = <1>;
1431				#size-cells = <0>;
1432
1433				port@0 {
1434					reg = <0>;
1435					hdmi_in: endpoint {
1436					};
1437				};
1438
1439				port@1 {
1440					reg = <1>;
1441					hdmi_out: endpoint {
1442					};
1443				};
1444			};
1445		};
1446
1447		hdmi_phy: hdmi-phy@4a00400 {
1448			compatible = "qcom,hdmi-phy-8960";
1449			reg = <0x4a00400 0x60>,
1450			      <0x4a00500 0x100>;
1451			reg-names = "hdmi_phy",
1452				    "hdmi_pll";
1453
1454			clocks = <&mmcc HDMI_S_AHB_CLK>;
1455			clock-names = "slave_iface_clk";
1456			#phy-cells = <0>;
1457		};
1458
1459		mdp: mdp@5100000 {
1460			compatible = "qcom,mdp4";
1461			reg = <0x05100000 0xf0000>;
1462			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1463			clocks = <&mmcc MDP_CLK>,
1464				 <&mmcc MDP_AHB_CLK>,
1465				 <&mmcc MDP_AXI_CLK>,
1466				 <&mmcc MDP_LUT_CLK>,
1467				 <&mmcc HDMI_TV_CLK>,
1468				 <&mmcc MDP_TV_CLK>;
1469			clock-names = "core_clk",
1470				      "iface_clk",
1471				      "bus_clk",
1472				      "lut_clk",
1473				      "hdmi_clk",
1474				      "tv_clk";
1475
1476			iommus = <&mdp_port0 0
1477				  &mdp_port0 2
1478				  &mdp_port1 0
1479				  &mdp_port1 2>;
1480
1481			ports {
1482				#address-cells = <1>;
1483				#size-cells = <0>;
1484
1485				port@0 {
1486					reg = <0>;
1487					mdp_lvds_out: endpoint {
1488					};
1489				};
1490
1491				port@1 {
1492					reg = <1>;
1493					mdp_dsi1_out: endpoint {
1494					};
1495				};
1496
1497				port@2 {
1498					reg = <2>;
1499					mdp_dsi2_out: endpoint {
1500					};
1501				};
1502
1503				port@3 {
1504					reg = <3>;
1505					mdp_dtv_out: endpoint {
1506					};
1507				};
1508			};
1509		};
1510
1511		riva: riva-pil@3204000 {
1512			compatible = "qcom,riva-pil";
1513
1514			reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1515			reg-names = "ccu", "dxe", "pmu";
1516
1517			interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1518					      <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1519			interrupt-names = "wdog", "fatal";
1520
1521			memory-region = <&wcnss_mem>;
1522
1523			vddcx-supply = <&pm8921_s3>;
1524			vddmx-supply = <&pm8921_l24>;
1525			vddpx-supply = <&pm8921_s4>;
1526
1527			status = "disabled";
1528
1529			iris {
1530				compatible = "qcom,wcn3660";
1531
1532				clocks = <&cxo_board>;
1533				clock-names = "xo";
1534
1535				vddxo-supply = <&pm8921_l4>;
1536				vddrfa-supply = <&pm8921_s2>;
1537				vddpa-supply = <&pm8921_l10>;
1538				vdddig-supply = <&pm8921_lvs2>;
1539			};
1540
1541			smd-edge {
1542				interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1543
1544				qcom,ipc = <&l2cc 8 25>;
1545				qcom,smd-edge = <6>;
1546
1547				label = "riva";
1548
1549				wcnss {
1550					compatible = "qcom,wcnss";
1551					qcom,smd-channels = "WCNSS_CTRL";
1552
1553					qcom,mmio = <&riva>;
1554
1555					bt {
1556						compatible = "qcom,wcnss-bt";
1557					};
1558
1559					wifi {
1560						compatible = "qcom,wcnss-wlan";
1561
1562						interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1563							     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1564						interrupt-names = "tx", "rx";
1565
1566						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1567						qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1568					};
1569				};
1570			};
1571		};
1572
1573		etb@1a01000 {
1574			compatible = "coresight-etb10", "arm,primecell";
1575			reg = <0x1a01000 0x1000>;
1576
1577			clocks = <&rpmcc RPM_QDSS_CLK>;
1578			clock-names = "apb_pclk";
1579
1580			in-ports {
1581				port {
1582					etb_in: endpoint {
1583						remote-endpoint = <&replicator_out0>;
1584					};
1585				};
1586			};
1587		};
1588
1589		tpiu@1a03000 {
1590			compatible = "arm,coresight-tpiu", "arm,primecell";
1591			reg = <0x1a03000 0x1000>;
1592
1593			clocks = <&rpmcc RPM_QDSS_CLK>;
1594			clock-names = "apb_pclk";
1595
1596			in-ports {
1597				port {
1598					tpiu_in: endpoint {
1599						remote-endpoint = <&replicator_out1>;
1600					};
1601				};
1602			};
1603		};
1604
1605		replicator {
1606			compatible = "arm,coresight-static-replicator";
1607
1608			clocks = <&rpmcc RPM_QDSS_CLK>;
1609			clock-names = "apb_pclk";
1610
1611			out-ports {
1612				#address-cells = <1>;
1613				#size-cells = <0>;
1614
1615				port@0 {
1616					reg = <0>;
1617					replicator_out0: endpoint {
1618						remote-endpoint = <&etb_in>;
1619					};
1620				};
1621				port@1 {
1622					reg = <1>;
1623					replicator_out1: endpoint {
1624						remote-endpoint = <&tpiu_in>;
1625					};
1626				};
1627			};
1628
1629			in-ports {
1630				port {
1631					replicator_in: endpoint {
1632						remote-endpoint = <&funnel_out>;
1633					};
1634				};
1635			};
1636		};
1637
1638		funnel@1a04000 {
1639			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1640			reg = <0x1a04000 0x1000>;
1641
1642			clocks = <&rpmcc RPM_QDSS_CLK>;
1643			clock-names = "apb_pclk";
1644
1645			in-ports {
1646				#address-cells = <1>;
1647				#size-cells = <0>;
1648
1649				/*
1650				 * Not described input ports:
1651				 * 2 - connected to STM component
1652				 * 3 - not-connected
1653				 * 6 - not-connected
1654				 * 7 - not-connected
1655				 */
1656				port@0 {
1657					reg = <0>;
1658					funnel_in0: endpoint {
1659						remote-endpoint = <&etm0_out>;
1660					};
1661				};
1662				port@1 {
1663					reg = <1>;
1664					funnel_in1: endpoint {
1665						remote-endpoint = <&etm1_out>;
1666					};
1667				};
1668				port@4 {
1669					reg = <4>;
1670					funnel_in4: endpoint {
1671						remote-endpoint = <&etm2_out>;
1672					};
1673				};
1674				port@5 {
1675					reg = <5>;
1676					funnel_in5: endpoint {
1677						remote-endpoint = <&etm3_out>;
1678					};
1679				};
1680			};
1681
1682			out-ports {
1683				port {
1684					funnel_out: endpoint {
1685						remote-endpoint = <&replicator_in>;
1686					};
1687				};
1688			};
1689		};
1690
1691		etm@1a1c000 {
1692			compatible = "arm,coresight-etm3x", "arm,primecell";
1693			reg = <0x1a1c000 0x1000>;
1694
1695			clocks = <&rpmcc RPM_QDSS_CLK>;
1696			clock-names = "apb_pclk";
1697
1698			cpu = <&CPU0>;
1699
1700			out-ports {
1701				port {
1702					etm0_out: endpoint {
1703						remote-endpoint = <&funnel_in0>;
1704					};
1705				};
1706			};
1707		};
1708
1709		etm@1a1d000 {
1710			compatible = "arm,coresight-etm3x", "arm,primecell";
1711			reg = <0x1a1d000 0x1000>;
1712
1713			clocks = <&rpmcc RPM_QDSS_CLK>;
1714			clock-names = "apb_pclk";
1715
1716			cpu = <&CPU1>;
1717
1718			out-ports {
1719				port {
1720					etm1_out: endpoint {
1721						remote-endpoint = <&funnel_in1>;
1722					};
1723				};
1724			};
1725		};
1726
1727		etm@1a1e000 {
1728			compatible = "arm,coresight-etm3x", "arm,primecell";
1729			reg = <0x1a1e000 0x1000>;
1730
1731			clocks = <&rpmcc RPM_QDSS_CLK>;
1732			clock-names = "apb_pclk";
1733
1734			cpu = <&CPU2>;
1735
1736			out-ports {
1737				port {
1738					etm2_out: endpoint {
1739						remote-endpoint = <&funnel_in4>;
1740					};
1741				};
1742			};
1743		};
1744
1745		etm@1a1f000 {
1746			compatible = "arm,coresight-etm3x", "arm,primecell";
1747			reg = <0x1a1f000 0x1000>;
1748
1749			clocks = <&rpmcc RPM_QDSS_CLK>;
1750			clock-names = "apb_pclk";
1751
1752			cpu = <&CPU3>;
1753
1754			out-ports {
1755				port {
1756					etm3_out: endpoint {
1757						remote-endpoint = <&funnel_in5>;
1758					};
1759				};
1760			};
1761		};
1762	};
1763};
1764#include "qcom-apq8064-pins.dtsi"
1765