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/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/
Dtqm5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
37 reg = <0x00000000 0x04000000>; // 64MB
44 ranges = <0 0xf0000000 0x0000c000>;
[all …]
Dcharon.dts23 #size-cells = <0>;
25 PowerPC,5200@0 {
27 reg = <0>;
30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
32 timebase-frequency = <0>; // from bootloader
33 bus-frequency = <0>; // from bootloader
34 clock-frequency = <0>; // from bootloader
40 reg = <0x00000000 0x08000000>; // 128MB
47 ranges = <0 0xf0000000 0x0000c000>;
[all …]
Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
37 reg = <0x00000000 0x04000000>; // 64MB
44 ranges = <0 0xf0000000 0x0000c000>;
[all …]
Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
38 reg = <0x00000000 0x04000000>; // 64MB
45 ranges = <0 0xf0000000 0x0000c000>;
[all …]
/Linux-v5.15/drivers/scsi/
Ddpti.h66 #define DPT_ORGANIZATION_ID (0x1B) /* For Private Messages */
76 #define EMPTY_QUEUE 0xffffffff
77 #define I2O_INTERRUPT_PENDING_B (0x08)
79 #define PCI_DPT_VENDOR_ID (0x1044) // DPT PCI Vendor ID
80 #define PCI_DPT_DEVICE_ID (0xA501) // DPT PCI I2O Device ID
81 #define PCI_DPT_RAPTOR_DEVICE_ID (0xA511)
102 #define FOREVER (0)
113 #define I2O_SCSI_DEVICE_DSC_MASK 0x00FF
115 #define I2O_DETAIL_STATUS_UNSUPPORTED_FUNCTION 0x000A
117 #define I2O_SCSI_DSC_MASK 0xFF00
[all …]
Dg_NCR5380.c69 #define NCR53C400_mem_base 0x3880
70 #define NCR53C400_host_buffer 0x3900
71 #define NCR53C400_region_size 0x3a00
73 #define BOARD_NCR5380 0
92 module_param_hw(ncr_irq, int, irq, 0);
93 module_param_hw(ncr_addr, int, ioport, 0);
94 module_param(ncr_5380, int, 0);
95 module_param(ncr_53c400, int, 0);
96 module_param(ncr_53c400a, int, 0);
97 module_param(dtc_3181e, int, 0);
[all …]
Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]
/Linux-v5.15/drivers/staging/media/atomisp/i2c/
Dov2722.h38 #define I2C_MSG_LENGTH 0x2
50 * bits 31-16: numerator, bits 15-0: denominator
52 #define OV2722_FOCAL_LENGTH_DEFAULT 0x1160064
56 * bits 31-16: numerator, bits 15-0: denominator
58 #define OV2722_F_NUMBER_DEFAULT 0x1a000a
65 * bits 7-0: min f-number denominator
67 #define OV2722_F_NUMBER_RANGE 0x1a0a1a0a
68 #define OV2720_ID 0x2720
69 #define OV2722_ID 0x2722
71 #define OV2722_FINE_INTG_TIME_MIN 0
[all …]
/Linux-v5.15/drivers/net/ethernet/amd/
Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/Linux-v5.15/drivers/gpu/drm/meson/
Dmeson_viu.c46 VIU_MATRIX_OSD_EOTF = 0,
51 VIU_LUT_OSD_EOTF = 0,
63 0, 0, 0, /* pre offset */
67 0, 0, 0, /* 10'/11'/12' */
68 0, 0, 0, /* 20'/21'/22' */
70 0, 0, 0 /* mode, right_shift, clip_en */
85 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_g12a_osd1_matrix()
87 writel(m[2] & 0xfff, in meson_viu_set_g12a_osd1_matrix()
89 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
91 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
[all …]
Dmeson_registers.h18 #define VPP2_DUMMY_DATA 0x1900
19 #define VPP2_LINE_IN_LENGTH 0x1901
20 #define VPP2_PIC_IN_HEIGHT 0x1902
21 #define VPP2_SCALE_COEF_IDX 0x1903
22 #define VPP2_SCALE_COEF 0x1904
23 #define VPP2_VSC_REGION12_STARTP 0x1905
24 #define VPP2_VSC_REGION34_STARTP 0x1906
25 #define VPP2_VSC_REGION4_ENDP 0x1907
26 #define VPP2_VSC_START_PHASE_STEP 0x1908
27 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909
[all …]
/Linux-v5.15/include/soc/fsl/qe/
Dimmap_qe.h25 u8 res0[0x04];
27 u8 res1[0x70];
43 u8 res0[0x4];
46 u8 res1[0x4];
48 u8 res2[0x20];
50 u8 res3[0x1C];
58 u8 res0[0xA];
60 u8 res1[0x2];
65 u8 res2[0x8];
69 u8 res3[0x2];
[all …]
/Linux-v5.15/drivers/net/ethernet/hisilicon/hns/
Dhns_dsaf_reg.h10 #define HNS_DEBUG_RING_IRQ_IDX 0
46 #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG 0x100
47 #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 0x180
48 #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG 0x184
49 #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG 0x188
50 #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG 0x18C
51 #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 0x190
52 #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG 0x194
53 #define DSAF_SUB_SC_DSAF_CLK_EN_REG 0x300
54 #define DSAF_SUB_SC_DSAF_CLK_DIS_REG 0x304
[all …]
/Linux-v5.15/include/linux/qed/
Dcommon_hsi.h16 #define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff))
23 } while (0)
47 #define ISCSI_CDU_TASK_SEG_TYPE 0
48 #define FCOE_CDU_TASK_SEG_TYPE 0
59 #define YSTORM_QZONE_SIZE 0
60 #define PSTORM_QZONE_SIZE 0
94 #define FW_ENGINEERING_VERSION 0
154 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
157 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
159 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
[all …]
/Linux-v5.15/drivers/media/i2c/
Dimx334.c20 #define IMX334_REG_MODE_SELECT 0x3000
21 #define IMX334_MODE_STANDBY 0x01
22 #define IMX334_MODE_STREAMING 0x00
25 #define IMX334_REG_LPFR 0x3030
28 #define IMX334_REG_ID 0x3044
29 #define IMX334_ID 0x1e
32 #define IMX334_REG_SHUTTER 0x3058
36 #define IMX334_EXPOSURE_DEFAULT 0x0648
39 #define IMX334_REG_AGAIN 0x30e8
40 #define IMX334_AGAIN_MIN 0
[all …]
Dimx335.c20 #define IMX335_REG_MODE_SELECT 0x3000
21 #define IMX335_MODE_STANDBY 0x01
22 #define IMX335_MODE_STREAMING 0x00
25 #define IMX335_REG_LPFR 0x3030
28 #define IMX335_REG_ID 0x3912
29 #define IMX335_ID 0x00
32 #define IMX335_REG_SHUTTER 0x3058
36 #define IMX335_EXPOSURE_DEFAULT 0x0648
39 #define IMX335_REG_AGAIN 0x30e8
40 #define IMX335_AGAIN_MIN 0
[all …]
Dov5648.c30 #define OV5648_SW_STANDBY_REG 0x100
31 #define OV5648_SW_STANDBY_STREAM_ON BIT(0)
33 #define OV5648_SW_RESET_REG 0x103
34 #define OV5648_SW_RESET_RESET BIT(0)
36 #define OV5648_PAD_OEN0_REG 0x3000
37 #define OV5648_PAD_OEN1_REG 0x3001
38 #define OV5648_PAD_OEN2_REG 0x3002
39 #define OV5648_PAD_OUT0_REG 0x3008
40 #define OV5648_PAD_OUT1_REG 0x3009
42 #define OV5648_CHIP_ID_H_REG 0x300a
[all …]
Dov5640.c32 #define OV5640_DEFAULT_SLAVE_ID 0x3c
34 #define OV5640_REG_SYS_RESET02 0x3002
35 #define OV5640_REG_SYS_CLOCK_ENABLE02 0x3006
36 #define OV5640_REG_SYS_CTRL0 0x3008
37 #define OV5640_REG_SYS_CTRL0_SW_PWDN 0x42
38 #define OV5640_REG_SYS_CTRL0_SW_PWUP 0x02
39 #define OV5640_REG_CHIP_ID 0x300a
40 #define OV5640_REG_IO_MIPI_CTRL00 0x300e
41 #define OV5640_REG_PAD_OUTPUT_ENABLE01 0x3017
42 #define OV5640_REG_PAD_OUTPUT_ENABLE02 0x3018
[all …]
/Linux-v5.15/drivers/net/ethernet/realtek/
Dr8169_phy_config.c23 int oldpage = phy_select_page(phydev, 0x0007); in r8168d_modify_extpage()
25 __phy_write(phydev, 0x1e, extpage); in r8168d_modify_extpage()
28 phy_restore_page(phydev, oldpage, 0); in r8168d_modify_extpage()
34 int oldpage = phy_select_page(phydev, 0x0005); in r8168d_phy_param()
36 __phy_write(phydev, 0x05, parm); in r8168d_phy_param()
37 __phy_modify(phydev, 0x06, mask, val); in r8168d_phy_param()
39 phy_restore_page(phydev, oldpage, 0); in r8168d_phy_param()
45 int oldpage = phy_select_page(phydev, 0x0a43); in r8168g_phy_param()
47 __phy_write(phydev, 0x13, parm); in r8168g_phy_param()
48 __phy_modify(phydev, 0x14, mask, val); in r8168g_phy_param()
[all …]
/Linux-v5.15/drivers/media/platform/rcar-vin/
Drcar-dma.c26 #define VNMC_REG 0x00 /* Video n Main Control Register */
27 #define VNMS_REG 0x04 /* Video n Module Status Register */
28 #define VNFC_REG 0x08 /* Video n Frame Capture Register */
29 #define VNSLPRC_REG 0x0C /* Video n Start Line Pre-Clip Register */
30 #define VNELPRC_REG 0x10 /* Video n End Line Pre-Clip Register */
31 #define VNSPPRC_REG 0x14 /* Video n Start Pixel Pre-Clip Register */
32 #define VNEPPRC_REG 0x18 /* Video n End Pixel Pre-Clip Register */
33 #define VNIS_REG 0x2C /* Video n Image Stride Register */
34 #define VNMB_REG(m) (0x30 + ((m) << 2)) /* Video n Memory Base m Register */
35 #define VNIE_REG 0x40 /* Video n Interrupt Enable Register */
[all …]
/Linux-v5.15/drivers/net/wireless/ath/ar5523/
Dar5523.c56 if (dlen < 0) { in ar5523_read_reply()
61 ar5523_dbg(ar, "Code = %d len = %d\n", be32_to_cpu(hdr->code) & 0xff, in ar5523_read_reply()
66 olen = be32_to_cpu(rp[0]); in ar5523_read_reply()
68 if (olen == 0) { in ar5523_read_reply()
69 /* convention is 0 =>'s one word */ in ar5523_read_reply()
73 olen = 0; in ar5523_read_reply()
79 cmd->olen = 0; in ar5523_read_reply()
84 cmd->res = 0; in ar5523_read_reply()
112 be32_to_cpu(hdr->code) & 0xff, hdr->priv); in ar5523_cmd_rx_cb()
117 switch (code & 0xff) { in ar5523_cmd_rx_cb()
[all …]
/Linux-v5.15/drivers/ata/
Data_piix.c34 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
51 * ICH2 errata #21 - DMA mode 0 doesn't work right
65 * (BIOS must set dev 31 fn 0 bit 23)
85 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
86 ICH5_PMR = 0x90, /* address map register */
87 ICH5_PCS = 0x92, /* port control and status */
90 PIIX_SIDPR_IDX = 0,
105 P0 = 0, /* port 0 */
156 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
158 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
[all …]
/Linux-v5.15/drivers/media/usb/go7007/
Dgo7007-fw.c40 #define SPECIAL_FRM_HEAD 0
58 #define CODE_GEN(name, dest) struct code_gen name = { dest, 0, 32, 0 }
70 } while (0)
169 { 0x01, 1 }, { 0x03, 3 }, { 0x02, 3 }, { 0x03, 4 },
170 { 0x02, 4 }, { 0x03, 5 }, { 0x02, 5 }, { 0x07, 7 },
171 { 0x06, 7 }, { 0x0b, 8 }, { 0x0a, 8 }, { 0x09, 8 },
172 { 0x08, 8 }, { 0x07, 8 }, { 0x06, 8 }, { 0x17, 10 },
173 { 0x16, 10 }, { 0x15, 10 }, { 0x14, 10 }, { 0x13, 10 },
174 { 0x12, 10 }, { 0x23, 11 }, { 0x22, 11 }, { 0x21, 11 },
175 { 0x20, 11 }, { 0x1f, 11 }, { 0x1e, 11 }, { 0x1d, 11 },
[all …]
/Linux-v5.15/sound/soc/mediatek/mt8195/
Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]

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