Lines Matching +full:0 +full:x3a00
16 #define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff))
23 } while (0)
47 #define ISCSI_CDU_TASK_SEG_TYPE 0
48 #define FCOE_CDU_TASK_SEG_TYPE 0
59 #define YSTORM_QZONE_SIZE 0
60 #define PSTORM_QZONE_SIZE 0
94 #define FW_ENGINEERING_VERSION 0
154 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
157 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
159 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
171 #define DQ_DEMS_LEGACY 0
177 #define DQ_XCM_AGG_VAL_SEL_WORD2 0
208 #define DQ_UCM_AGG_VAL_SEL_WORD0 0
224 #define DQ_TCM_AGG_VAL_SEL_WORD0 0
240 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0
265 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0
284 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0
303 #define DQ_PWM_OFFSET_DPM_BASE 0x0
304 #define DQ_PWM_OFFSET_DPM_END 0x27
305 #define DQ_PWM_OFFSET_XCM16_BASE 0x40
306 #define DQ_PWM_OFFSET_XCM32_BASE 0x44
307 #define DQ_PWM_OFFSET_UCM16_BASE 0x48
308 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C
309 #define DQ_PWM_OFFSET_UCM16_4 0x50
310 #define DQ_PWM_OFFSET_TCM16_BASE 0x58
311 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C
312 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68
313 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69
314 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B
359 #define CM_TX_PQ_BASE 0x200
378 #define CAU_FSM_ETH_RX 0
387 #define CAU_HC_ENABLE_STATE 0
403 #define IGU_MEM_BASE 0x0000
405 #define IGU_MEM_MSIX_BASE 0x0000
406 #define IGU_MEM_MSIX_UPPER 0x0101
407 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
409 #define IGU_MEM_PBA_MSIX_BASE 0x0200
410 #define IGU_MEM_PBA_MSIX_UPPER 0x0202
411 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
413 #define IGU_CMD_INT_ACK_BASE 0x0400
414 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
416 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
417 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1
418 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2
420 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3
421 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4
422 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5
423 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6
425 #define IGU_CMD_PROD_UPD_BASE 0x0600
426 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff
433 #define PXP_BAR_GRC 0
434 #define PXP_BAR_TSDM 0
435 #define PXP_BAR_USDM 0
436 #define PXP_BAR_XSDM 0
437 #define PXP_BAR_MSDM 0
438 #define PXP_BAR_YSDM 0
439 #define PXP_BAR_PSDM 0
440 #define PXP_BAR_IGU 0
448 #define PXP_PF_WINDOW_ADMIN_START 0
449 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000
452 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0
457 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200
463 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0
464 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4
465 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8
466 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc
469 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000
471 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000
482 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000
491 #define PXP_BAR0_START_GRC 0x0000
492 #define PXP_BAR0_GRC_LENGTH 0x1C00000
496 #define PXP_BAR0_START_IGU 0x1C00000
497 #define PXP_BAR0_IGU_LENGTH 0x10000
501 #define PXP_BAR0_START_TSDM 0x1C80000
502 #define PXP_BAR0_SDM_LENGTH 0x40000
503 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000
507 #define PXP_BAR0_START_MSDM 0x1D00000
511 #define PXP_BAR0_START_USDM 0x1D80000
515 #define PXP_BAR0_START_XSDM 0x1E00000
519 #define PXP_BAR0_START_YSDM 0x1E80000
523 #define PXP_BAR0_START_PSDM 0x1F00000
530 #define PXP_VF_BAR0 0
532 #define PXP_VF_BAR0_START_IGU 0
533 #define PXP_VF_BAR0_IGU_LENGTH 0x3000
537 #define PXP_VF_BAR0_START_DQ 0x3000
538 #define PXP_VF_BAR0_DQ_LENGTH 0x200
539 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0
547 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200
548 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200
552 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400
556 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600
560 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800
564 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00
568 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00
572 #define PXP_VF_BAR0_START_GRC 0x3E00
573 #define PXP_VF_BAR0_GRC_LENGTH 0x200
577 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
578 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
580 #define PXP_VF_BAR0_START_IGU2 0x10000
581 #define PXP_VF_BAR0_IGU2_LENGTH 0xD000
607 #define SDM_OP_GEN_TRIG_NONE 0
618 #define SDM_COMP_TYPE_NONE 0
648 #define COALESCING_TIMESET_TIMESET_MASK 0x7F
649 #define COALESCING_TIMESET_TIMESET_SHIFT 0
650 #define COALESCING_TIMESET_VALID_MASK 0x1
669 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK 0x1
670 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT 0
671 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK 0x7F
687 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F
688 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0
689 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1
691 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1
755 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF
756 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0
757 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F
759 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1
761 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF
768 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF
769 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0
770 #define CAU_SB_ENTRY_STATE0_MASK 0xF
772 #define CAU_SB_ENTRY_STATE1_MASK 0xF
775 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F
776 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
777 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F
779 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3
781 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3
783 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF
785 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1
787 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF
789 #define CAU_SB_ENTRY_TPH_MASK 0x1
797 IGU_COMMAND_TYPE_NOP = 0,
805 #define CORE_DB_DATA_DEST_MASK 0x3
806 #define CORE_DB_DATA_DEST_SHIFT 0
807 #define CORE_DB_DATA_AGG_CMD_MASK 0x3
809 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1
811 #define CORE_DB_DATA_RESERVED_MASK 0x1
813 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3
851 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F
852 #define DB_L2_DPM_DATA_SIZE_SHIFT 0
853 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3
855 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF
857 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF
859 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1
861 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7
863 #define DB_L2_DPM_DATA_TGFS_SRC_EN_MASK 0x1
872 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF
873 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
874 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3
876 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1
878 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF
886 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3
887 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
888 #define DB_LEGACY_ADDR_DEMS_MASK 0x7
890 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF
897 #define DB_PWM_ADDR_RESERVED0_MASK 0x7
898 #define DB_PWM_ADDR_RESERVED0_SHIFT 0
899 #define DB_PWM_ADDR_OFFSET_MASK 0x7F
901 #define DB_PWM_ADDR_WID_MASK 0x3
903 #define DB_PWM_ADDR_DPI_MASK 0xFFFF
905 #define DB_PWM_ADDR_RESERVED1_MASK 0xF
912 #define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F
913 #define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0
914 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3
916 #define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF
918 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
920 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1
922 #define DB_RDMA_DPM_PARAMS_ACK_REQUEST_MASK 0x1
924 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1
926 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
928 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1
943 IGU_INT_ENABLE = 0,
953 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF
954 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0
955 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1
957 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3
959 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1
961 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1
963 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3
965 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1
972 IGU_SEG_ACCESS_REG = 0,
978 * L3Type: 0 - unknown (not ip), 1 - Ipv4, 2 - Ipv6
989 * L4-protocol: 0 - none, 1 - TCP, 2 - UDP.
1003 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3
1004 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0
1005 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3
1007 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1
1009 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1
1011 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1
1013 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1
1015 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1
1017 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1
1019 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1
1021 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1
1023 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1
1025 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1
1027 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1
1029 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1
1036 #define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1
1037 #define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0
1038 #define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1
1040 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1
1042 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1
1044 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1
1046 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1
1048 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1
1050 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1
1052 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1
1054 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1
1056 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK 0x1
1058 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1
1060 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1
1062 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1
1064 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1
1066 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1
1078 #define PXP_CONCRETE_FID_PFID_MASK 0xF
1079 #define PXP_CONCRETE_FID_PFID_SHIFT 0
1080 #define PXP_CONCRETE_FID_PORT_MASK 0x3
1082 #define PXP_CONCRETE_FID_PATH_MASK 0x1
1084 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1
1086 #define PXP_CONCRETE_FID_VFID_MASK 0xFF
1093 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF
1094 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0
1095 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7
1097 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1
1099 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF
1113 #define PXP_PRETEND_CMD_PATH_MASK 0x1
1114 #define PXP_PRETEND_CMD_PATH_SHIFT 0
1115 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1
1117 #define PXP_PRETEND_CMD_PORT_MASK 0x3
1119 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF
1121 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF
1123 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1
1125 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1
1127 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1
1129 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1
1136 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF
1137 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0
1138 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF
1146 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
1147 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0
1148 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1
1150 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F
1152 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF
1162 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
1163 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
1164 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
1166 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
1168 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
1170 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
1172 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
1174 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
1181 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
1182 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
1183 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
1185 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
1187 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
1189 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
1191 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
1193 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
1195 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
1197 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
1199 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
1201 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
1203 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
1205 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
1208 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF
1209 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0
1210 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF
1212 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1
1214 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1
1216 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
1218 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
1227 #define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF
1228 #define STATUS_BLOCK_E4_SB_NUM_SHIFT 0
1229 #define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F
1231 #define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF
1234 #define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF
1235 #define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0
1236 #define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF
1248 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF
1249 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0
1250 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF
1252 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1
1254 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1
1256 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
1260 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
1261 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
1262 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
1264 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
1266 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
1268 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
1270 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
1272 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
1275 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
1276 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
1277 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
1279 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
1281 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
1283 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
1285 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
1287 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
1289 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
1291 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
1293 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1
1295 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
1297 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF
1299 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF
1301 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1
1303 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1
1305 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
1307 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
1309 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
1311 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
1313 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
1326 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF
1327 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0
1328 #define TIMERS_CONTEXT_RESERVED0_MASK 0x1
1330 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1
1332 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1
1334 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3
1337 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF
1338 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0
1339 #define TIMERS_CONTEXT_RESERVED2_MASK 0x1
1341 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1
1343 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1
1345 #define TIMERS_CONTEXT_RESERVED3_MASK 0x3
1348 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF
1349 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0
1350 #define TIMERS_CONTEXT_RESERVED4_MASK 0x1
1352 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1
1354 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1
1356 #define TIMERS_CONTEXT_RESERVED5_MASK 0x3
1359 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF
1360 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0
1361 #define TIMERS_CONTEXT_RESERVED6_MASK 0x1
1363 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1
1365 #define TIMERS_CONTEXT_RESERVED7_MASK 0x7
1371 e_unknown = 0,