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/Linux-v5.10/drivers/pinctrl/berlin/
Dberlin-bg4ct.c18 BERLIN_PINCTRL_GROUP("EMMC_RSTn", 0x0, 0x3, 0x00,
19 BERLIN_PINCTRL_FUNCTION(0x0, "emmc"), /* RSTn */
20 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* GPIO47 */
21 BERLIN_PINCTRL_GROUP("NAND_IO0", 0x0, 0x3, 0x03,
22 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO0 */
23 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD0 */
24 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CLK */
25 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO0 */
26 BERLIN_PINCTRL_GROUP("NAND_IO1", 0x0, 0x3, 0x06,
27 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO1 */
[all …]
Dpinctrl-as370.c18 BERLIN_PINCTRL_GROUP("I2S1_BCLKIO", 0x0, 0x3, 0x00,
19 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO0 */
20 BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* BCLKIO */
21 BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG0 */
22 BERLIN_PINCTRL_GROUP("I2S1_LRCKIO", 0x0, 0x3, 0x03,
23 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO1 */
24 BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* LRCKIO */
25 BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG1 */
26 BERLIN_PINCTRL_GROUP("I2S1_DO0", 0x0, 0x3, 0x06,
27 BERLIN_PINCTRL_FUNCTION(0x0, "por"), /* 1P8V RSTB*/
[all …]
Dberlin-bg2q.c19 BERLIN_PINCTRL_GROUP("G0", 0x18, 0x3, 0x00,
20 BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
21 BERLIN_PINCTRL_FUNCTION(0x1, "mmc"),
22 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
23 BERLIN_PINCTRL_GROUP("G1", 0x18, 0x3, 0x03,
24 BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
25 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
26 BERLIN_PINCTRL_GROUP("G2", 0x18, 0x3, 0x06,
27 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
28 BERLIN_PINCTRL_FUNCTION(0x2, "arc"),
[all …]
Dberlin-bg2cd.c19 BERLIN_PINCTRL_GROUP("G0", 0x00, 0x3, 0x00,
20 BERLIN_PINCTRL_FUNCTION(0x0, "jtag"),
21 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"),
22 BERLIN_PINCTRL_FUNCTION(0x2, "led"),
23 BERLIN_PINCTRL_FUNCTION(0x3, "pwm")),
24 BERLIN_PINCTRL_GROUP("G1", 0x00, 0x3, 0x03,
25 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
26 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
27 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
28 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
[all …]
/Linux-v5.10/arch/x86/crypto/
Dserpent-avx2-asm_64.S21 .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
26 .byte 0x87, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0
31 .byte 0x0e, 1, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0
61 #define S0_1(x0, x1, x2, x3, x4) \ argument
62 vpor x0, x3, tp; \
63 vpxor x3, x0, x0; \
64 vpxor x2, x3, x4; \
66 vpxor x1, tp, x3; \
70 #define S0_2(x0, x1, x2, x3, x4) \ argument
71 vpxor x3, x0, x0; \
[all …]
Dserpent-avx-x86_64-asm_64.S20 .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
24 .byte 0x87, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0
55 #define S0_1(x0, x1, x2, x3, x4) \ argument
56 vpor x0, x3, tp; \
57 vpxor x3, x0, x0; \
58 vpxor x2, x3, x4; \
60 vpxor x1, tp, x3; \
64 #define S0_2(x0, x1, x2, x3, x4) \ argument
65 vpxor x3, x0, x0; \
69 vpxor x2, x3, x3; \
[all …]
Dserpent-sse2-i586-asm_32.S40 pshufd $0, t, t;
42 #define K(x0, x1, x2, x3, x4, i) \ argument
43 get_key(i, 0, x4); \
50 pxor x4, x3;
52 #define LK(x0, x1, x2, x3, x4, i) \ argument
69 pxor x2, x3; \
70 pxor x4, x3; \
71 movdqa x3, x4; \
72 pslld $7, x3; \
74 por x4, x3; \
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/Linux-v5.10/arch/arm64/boot/dts/freescale/
Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/Linux-v5.10/drivers/pinctrl/sunxi/
Dpinctrl-sun4i-a10.c22 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
23 SUNXI_FUNCTION(0x0, "gpio_in"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
26 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
27 SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
28 SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD3 */
32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
[all …]
Dpinctrl-suniv-f1c100s.c33 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
34 SUNXI_FUNCTION(0x0, "gpio_in"),
35 SUNXI_FUNCTION(0x1, "gpio_out"),
36 SUNXI_FUNCTION(0x2, "rtp"), /* X1 */
37 SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
38 SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
39 SUNXI_FUNCTION(0x6, "spi1")), /* CS */
41 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out"),
43 SUNXI_FUNCTION(0x2, "rtp"), /* X2 */
[all …]
/Linux-v5.10/include/linux/mfd/syscon/
Dimx6q-iomuxc-gpr.h11 #define IOMUXC_GPR0 0x00
12 #define IOMUXC_GPR1 0x04
13 #define IOMUXC_GPR2 0x08
14 #define IOMUXC_GPR3 0x0c
15 #define IOMUXC_GPR4 0x10
16 #define IOMUXC_GPR5 0x14
17 #define IOMUXC_GPR6 0x18
18 #define IOMUXC_GPR7 0x1c
19 #define IOMUXC_GPR8 0x20
20 #define IOMUXC_GPR9 0x24
[all …]
/Linux-v5.10/include/dt-bindings/mux/
Dti-serdes.h11 #define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0
12 #define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
13 #define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2
14 #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
16 #define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0
17 #define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
18 #define J721E_SERDES0_LANE1_USB3_0 0x2
19 #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
21 #define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0
22 #define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1
[all …]
/Linux-v5.10/arch/arm64/lib/
Dtishift.S12 mov x3, #64
13 sub x3, x3, x2
14 cmp x3, #0
17 lsr x3, x0, x3
19 orr x1, x1, x3
25 mov x2, #0
34 mov x3, #64
35 sub x3, x3, x2
36 cmp x3, #0
39 lsl x3, x1, x3
[all …]
/Linux-v5.10/crypto/
Dserpent_generic.c27 #define PHI 0x9e3779b9UL
32 #define loadkeys(x0, x1, x2, x3, i) \ argument
33 ({ x0 = k[i]; x1 = k[i+1]; x2 = k[i+2]; x3 = k[i+3]; })
35 #define storekeys(x0, x1, x2, x3, i) \ argument
36 ({ k[i] = x0; k[i+1] = x1; k[i+2] = x2; k[i+3] = x3; })
38 #define store_and_load_keys(x0, x1, x2, x3, s, l) \ argument
39 ({ storekeys(x0, x1, x2, x3, s); loadkeys(x0, x1, x2, x3, l); })
41 #define K(x0, x1, x2, x3, i) ({ \ argument
42 x3 ^= k[4*(i)+3]; x2 ^= k[4*(i)+2]; \
43 x1 ^= k[4*(i)+1]; x0 ^= k[4*(i)+0]; \
[all …]
/Linux-v5.10/drivers/clk/mmp/
Dclk-of-pxa1928.c26 #define MPMU_UART_PLL 0x14
37 {0, "clk32", NULL, 0, 32768},
38 {0, "vctcxo", NULL, 0, 26000000},
39 {0, "pll1_624", NULL, 0, 624000000},
40 {0, "pll5p", NULL, 0, 832000000},
41 {0, "pll5", NULL, 0, 1248000000},
42 {0, "usb_pll", NULL, 0, 480000000},
46 {0, "pll1_d2", "pll1_624", 1, 2, 0},
47 {0, "pll1_d9", "pll1_624", 1, 9, 0},
48 {0, "pll1_d12", "pll1_624", 1, 12, 0},
[all …]
Dclk-of-pxa168.c25 #define APBC_RTC 0x28
26 #define APBC_TWSI0 0x2c
27 #define APBC_KPC 0x30
28 #define APBC_UART0 0x0
29 #define APBC_UART1 0x4
30 #define APBC_GPIO 0x8
31 #define APBC_PWM0 0xc
32 #define APBC_PWM1 0x10
33 #define APBC_PWM2 0x14
34 #define APBC_PWM3 0x18
[all …]
/Linux-v5.10/drivers/net/wireless/mediatek/mt76/mt76x0/
Dinitvals_phy.h12 { MT_RF(0, 1), 0x01 },
13 { MT_RF(0, 2), 0x11 },
15 { MT_RF(0, 3), 0x73 }, /* VCO Freq Cal */
16 { MT_RF(0, 4), 0x30 }, /* R4 b<7>=1, VCO cal */
17 { MT_RF(0, 5), 0x00 },
18 { MT_RF(0, 6), 0x41 },
19 { MT_RF(0, 7), 0x00 },
20 { MT_RF(0, 8), 0x00 },
21 { MT_RF(0, 9), 0x00 },
22 { MT_RF(0, 10), 0x0C },
[all …]
/Linux-v5.10/arch/arm/mach-omap2/
Dprm-regbits-33xx.h21 #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17)
23 #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4)
25 #define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
26 #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5)
28 #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23)
30 #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
37 #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18)
39 #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6)
40 #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20)
42 #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8)
[all …]
Dcm-regbits-34xx.h14 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0)
15 #define OMAP3430_ST_IVA2_SHIFT 0
16 #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
17 #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
18 #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
28 #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
29 #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
30 #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
31 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
32 #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
[all …]

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