Lines Matching +full:0 +full:x3
25 #define APBC_RTC 0x28
26 #define APBC_TWSI0 0x2c
27 #define APBC_KPC 0x30
28 #define APBC_UART0 0x0
29 #define APBC_UART1 0x4
30 #define APBC_GPIO 0x8
31 #define APBC_PWM0 0xc
32 #define APBC_PWM1 0x10
33 #define APBC_PWM2 0x14
34 #define APBC_PWM3 0x18
35 #define APBC_TIMER 0x34
36 #define APBC_SSP0 0x81c
37 #define APBC_SSP1 0x820
38 #define APBC_SSP2 0x84c
39 #define APBC_SSP3 0x858
40 #define APBC_SSP4 0x85c
41 #define APBC_TWSI1 0x6c
42 #define APBC_UART2 0x70
43 #define APMU_SDH0 0x54
44 #define APMU_SDH1 0x58
45 #define APMU_USB 0x5c
46 #define APMU_DISP0 0x4c
47 #define APMU_CCIC0 0x50
48 #define APMU_DFC 0x60
49 #define MPMU_UART_PLL 0x14
59 {PXA168_CLK_CLK32, "clk32", NULL, 0, 32768},
60 {PXA168_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
61 {PXA168_CLK_PLL1, "pll1", NULL, 0, 624000000},
62 {PXA168_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
66 {PXA168_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
67 {PXA168_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
68 {PXA168_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
69 {PXA168_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
70 {PXA168_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
71 {PXA168_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
72 {PXA168_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
73 {PXA168_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
74 {PXA168_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
75 {PXA168_CLK_PLL1_192, "pll1_192", "pll1_96", 1, 2, 0},
76 {PXA168_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
77 {PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
78 {PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
79 {PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
84 .num_mask = 0x1fff,
85 .den_mask = 0x1fff,
87 .den_shift = 0,
131 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
132 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
133 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2…
134 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
135 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
136 …{0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4,…
137 …{0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4,…
138 …{0, "ssp4_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP4, 4,…
139 …{0, "timer_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIM…
143 …{PXA168_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, …
144 …{PXA168_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x3, 0x3, 0x0, 0, …
145 …{PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_l…
146 …{PXA168_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NE…
147 …{PXA168_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_…
148 …{PXA168_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_…
149 …{PXA168_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_…
150 …{PXA168_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_…
151 …{PXA168_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_…
153 …{PXA168_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &u…
154 …{PXA168_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &u…
155 …{PXA168_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x3, 0x3, 0x0, 0, &u…
156 …{PXA168_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_…
157 …{PXA168_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_…
158 …{PXA168_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x3, 0x3, 0x0, 0, &ssp2_…
159 …{PXA168_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x3, 0x3, 0x0, 0, &ssp3_…
160 …{PXA168_CLK_SSP4, "ssp4_clk", "ssp4_mux", CLK_SET_RATE_PARENT, APBC_SSP4, 0x3, 0x3, 0x0, 0, &ssp4_…
161 …{PXA168_CLK_TIMER, "timer_clk", "timer_mux", CLK_SET_RATE_PARENT, APBC_TIMER, 0x3, 0x3, 0x0, 0, &t…
190 …{0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6,…
191 …{0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6,…
192 …{0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0…
193 …{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0…
194 …{0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT…
198 {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
202 {PXA168_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
203 {PXA168_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
204 {PXA168_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
206 …{PXA168_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh…
207 …{PXA168_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh…
208 …{PXA168_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, …
209 …{PXA168_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, …
210 …"ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock…
211 …ic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_loc…
239 for (i = 0; i < nr_resets; i++) { in pxa168_clk_reset_init()
242 cells[i].flags = 0; in pxa168_clk_reset_init()
244 cells[i].bits = 0x4; in pxa168_clk_reset_init()
258 pxa_unit->mpmu_base = of_iomap(np, 0); in pxa168_clk_init()