Home
last modified time | relevance | path

Searched +full:0 +full:x2e000000 (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.10/Documentation/devicetree/bindings/mailbox/
Darm,mhu.yaml98 reg = <0 0x2b1f0000 0 0x1000>;
99 interrupts = <0 36 4>, /* LP-NonSecure */
100 <0 35 4>, /* HP-NonSecure */
101 <0 37 4>; /* Secure */
102 clocks = <&clock 0 2 1>;
108 reg = <0 0x2e000000 0 0x4000>;
122 reg = <0 0x2b2f0000 0 0x1000>;
123 interrupts = <0 36 4>, /* LP-NonSecure */
124 <0 35 4>, /* HP-NonSecure */
125 <0 37 4>; /* Secure */
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic-v3.yaml33 enum: [ 0, 1, 2 ]
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extented SPI interrupts are in the range [0-1023].
53 Extended PPI interrupts are in the range [0-127].
56 bits[3:0] trigger type and level flags.
68 of 0 if present.
95 multipleOf: 0x10000
96 exclusiveMinimum: 0
136 "^interrupt-partition-[0-9]+$":
[all …]
/Linux-v5.10/arch/arm64/boot/dts/arm/
Djuno-base.dtsi12 reg = <0x0 0x2a810000 0x0 0x10000>;
16 ranges = <0 0x0 0x2a820000 0x20000>;
21 reg = <0x10000 0x10000>;
27 reg = <0x0 0x2b1f0000 0x0 0x1000>;
39 reg = <0x0 0x2b400000 0x0 0x10000>;
51 reg = <0x0 0x2b500000 0x0 0x10000>;
62 reg = <0x0 0x2b600000 0x0 0x10000>;
68 power-domains = <&scpi_devpd 0>;
73 reg = <0x0 0x2c010000 0 0x1000>,
74 <0x0 0x2c02f000 0 0x2000>,
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dqcom-ipq8064.dtsi21 #size-cells = <0>;
23 cpu@0 {
27 reg = <0>;
51 reg = <0x0 0x0>;
66 reg = <0x40000000 0x1000000>;
71 reg = <0x41000000 0x200000>;
79 #clock-cells = <0>;
85 #clock-cells = <0>;
92 #clock-cells = <0>;
119 reg = <0x28100000 0x10000>;
[all …]
/Linux-v5.10/drivers/net/ethernet/sgi/
Dmeth.h24 u64 pad0:34;/* always set to 0 */
32 * It consists of header, 0-3 concatination
36 u64 pad1:36; /*should be filled with 0 */
47 u64 pad2:16; /* should be 0 */
70 u64 pad2:15;/*fill with 0*/
96 #define TX_INFO_RPTR 0x00FF0000
97 #define TX_INFO_WPTR 0x000000FF
101 #define SGI_MAC_RESET BIT(0) /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 cor…
102 #define METH_PHY_FDX BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */
103 #define METH_PHY_LOOP BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loo…
[all …]
/Linux-v5.10/arch/hexagon/kernel/
Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/Linux-v5.10/crypto/
Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_7_0_default.h26 #define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000
29 #define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000
30 #define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000
31 #define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000
32 #define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000
34 #define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgNB_NBCFG0_NB_LATENCY_DEFAULT 0x00000000
[all …]
Dnbio_6_1_default.h26 #define cfgPSWUSCFG0_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgPSWUSCFG0_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgPSWUSCFG0_COMMAND_DEFAULT 0x00000000
29 #define cfgPSWUSCFG0_STATUS_DEFAULT 0x00000000
30 #define cfgPSWUSCFG0_REVISION_ID_DEFAULT 0x00000000
31 #define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT 0x00000000
32 #define cfgPSWUSCFG0_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgPSWUSCFG0_BASE_CLASS_DEFAULT 0x00000000
34 #define cfgPSWUSCFG0_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgPSWUSCFG0_LATENCY_DEFAULT 0x00000000
[all …]