Lines Matching +full:0 +full:x2e000000
21 #size-cells = <0>;
23 cpu@0 {
27 reg = <0>;
51 reg = <0x0 0x0>;
66 reg = <0x40000000 0x1000000>;
71 reg = <0x41000000 0x200000>;
79 #clock-cells = <0>;
85 #clock-cells = <0>;
92 #clock-cells = <0>;
119 reg = <0x28100000 0x10000>;
125 reg = <0x800000 0x4000>;
128 gpio-ranges = <&qcom_pinmux 0 0 69>;
194 reg = <0x02000000 0x1000>,
195 <0x02002000 0x1000>;
211 reg = <0x0200a000 0x100>;
216 cpu-offset = <0x80000>;
221 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
226 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
231 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
237 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
244 reg = <0x12480000 0x100>;
256 reg = <0x12490000 0x1000>,
257 <0x12480000 0x1000>;
266 reg = <0x124a0000 0x1000>;
274 #size-cells = <0>;
282 reg = <0x16300000 0x100>;
294 reg = <0x16340000 0x1000>,
295 <0x16300000 0x1000>;
304 reg = <0x16380000 0x1000>;
312 #size-cells = <0>;
319 reg = <0x1a200000 0x100>;
331 reg = <0x1a240000 0x1000>,
332 <0x1a200000 0x1000>;
341 reg = <0x1a280000 0x1000>;
349 #size-cells = <0>;
354 reg = <0x1a280000 0x1000>;
362 #size-cells = <0>;
370 reg = <0x16600000 0x100>;
380 reg = <0x16640000 0x1000>,
381 <0x16600000 0x1000>;
391 reg = <0x1b400000 0x200>;
396 #phy-cells = <0>;
402 reg = <0x29000000 0x180>;
424 reg = <0x00500000 0x1000>;
430 reg = <0x00700000 0x1000>;
437 reg = <0x00900000 0x4000>;
444 reg = <0x1a400000 0x100>;
449 reg = <0x28000000 0x1000>;
456 reg = <0x1b500000 0x1000
457 0x1b502000 0x80
458 0x1b600000 0x100
459 0x0ff00000 0x100000>;
462 linux,pci-domain = <0>;
463 bus-range = <0x00 0xff>;
468 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
469 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
474 interrupt-map-mask = <0 0 0 0x7>;
475 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
476 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
477 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
478 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
498 pinctrl-0 = <&pcie0_pins>;
507 reg = <0x1b700000 0x1000
508 0x1b702000 0x80
509 0x1b800000 0x100
510 0x31f00000 0x100000>;
514 bus-range = <0x00 0xff>;
519 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
520 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
525 interrupt-map-mask = <0 0 0 0x7>;
526 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
527 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
528 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
529 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
549 pinctrl-0 = <&pcie1_pins>;
558 reg = <0x1b900000 0x1000
559 0x1b902000 0x80
560 0x1ba00000 0x100
561 0x35f00000 0x100000>;
565 bus-range = <0x00 0xff>;
570 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
571 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
576 interrupt-map-mask = <0 0 0 0x7>;
577 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
578 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
579 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
580 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
600 pinctrl-0 = <&pcie2_pins>;
609 reg = <0x03000000 0x0000FFFF>;
614 reg = <0x1bb00000 0x000001FF>;
620 snps,blen = <16 0 0 0 0 0 0>;
626 reg = <0x37000000 0x200000>;
649 reg = <0x37200000 0x200000>;
672 reg = <0x37400000 0x200000>;
695 reg = <0x37600000 0x200000>;
725 reg = <0x12402000 0x8000>;
730 qcom,ee = <0>;
735 reg = <0x12182000 0x8000>;
740 qcom,ee = <0>;
752 arm,primecell-periphid = <0x00051180>;
753 reg = <0x12400000 0x2000>;
771 arm,primecell-periphid = <0x00051180>;
773 reg = <0x12180000 0x2000>;