Lines Matching +full:0 +full:x2e000000
24 u64 pad0:34;/* always set to 0 */
32 * It consists of header, 0-3 concatination
36 u64 pad1:36; /*should be filled with 0 */
47 u64 pad2:16; /* should be 0 */
70 u64 pad2:15;/*fill with 0*/
96 #define TX_INFO_RPTR 0x00FF0000
97 #define TX_INFO_WPTR 0x000000FF
101 #define SGI_MAC_RESET BIT(0) /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 cor…
102 #define METH_PHY_FDX BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */
103 #define METH_PHY_LOOP BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loo…
105 #define METH_100MBIT BIT(3) /* 0: 10meg mode, 1: 100meg mode */
106 #define METH_PHY_MII BIT(4) /* 0: MII selected, 1: SIA selected */
111 #define METH_ACCEPT_MY 0 /* 00: Accept PHY address only */
112 #define METH_ACCEPT_MCAST 0x20 /* 01: Accept physical, broadcast, and multicast filter matches only…
113 #define METH_ACCEPT_AMCAST 0x40 /* 10: Accept physical, broadcast, and all multicast packets */
114 #define METH_PROMISC 0x60 /* 11: Promiscious mode */
116 #define METH_PHY_LINK_FAIL BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link…
118 #define METH_MAC_IPG 0x1ffff00
121 /* 0x172e5c00 */ /* 23, 23, 23 */ /*0x54A9500 *//*21,21,21*/
140 #define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */
145 #define METH_RX_FIFO_WPTR(x) (((x)>>16)&0xf)
146 #define METH_RX_FIFO_RPTR(x) (((x)>>8)&0xf)
147 #define METH_RX_FIFO_DEPTH(x) ((x)&0x1f)
175 #define METH_INT_TX_EMPTY BIT(0) /* 0: No interrupt pending, 1: The TX ring buffer is empty */
176 #define METH_INT_TX_PKT BIT(1) /* 0: No interrupt pending */
178 #define METH_INT_TX_LINK_FAIL BIT(2) /* 0: No interrupt pending, 1: PHY has reported a link failure…
179 #define METH_INT_MEM_ERROR BIT(3) /* 0: No interrupt pending */
181 #define METH_INT_TX_ABORT BIT(4) /* 0: No interrupt pending, 1: The TX aborted operation, DMA stop…
182 #define METH_INT_RX_THRESHOLD BIT(5) /* 0: No interrupt pending, 1: Selected receive threshold cond…
183 #define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could no…
184 #define METH_INT_RX_OVERFLOW BIT(7) /* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped,…
186 /*#define METH_INT_RX_RPTR_MASK 0x0001F00*/ /* Bits 8 through 12 alias of RX read-pointer */
187 #define METH_INT_RX_RPTR_MASK 0x0000F00 /* Bits 8 through 11 alias of RX read-pointer - so, is Rx …
189 /* Bits 13 through 15 are always 0. */
191 #define METH_INT_TX_RPTR_MASK 0x1FF0000 /* Bits 16 through 24 alias of TX read-pointer */
193 #define METH_INT_RX_SEQ_MASK 0x2E000000 /* Bits 25 through 29 are the starting seq number for the m…
220 #define MDIO_DATA_MASK 0xFFFF
222 #define PHY_QS6612X 0x0181441 /* Quality TX */
223 #define PHY_ICS1889 0x0015F41 /* ICS FX */
224 #define PHY_ICS1890 0x0015F42 /* ICS TX */
225 #define PHY_DP83840 0x20005C0 /* National TX */