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/Linux-v6.1/drivers/gpu/drm/ast/
Dast_dram_tables.h12 { 0x0108, 0x00000000 },
13 { 0x0120, 0x00004a21 },
14 { 0xFF00, 0x00000043 },
15 { 0x0000, 0xFFFFFFFF },
16 { 0x0004, 0x00000089 },
17 { 0x0008, 0x22331353 },
18 { 0x000C, 0x0d07000b },
19 { 0x0010, 0x11113333 },
20 { 0x0020, 0x00110350 },
21 { 0x0028, 0x1e0828f0 },
[all …]
/Linux-v6.1/arch/sh/include/mach-landisk/mach/
Diodata_landisk.h16 #define PA_USB 0xa4000000 /* USB Controller M66590 */
18 #define PA_ATARST 0xb0000000 /* ATA/FATA Access Control Register */
19 #define PA_LED 0xb0000001 /* LED Control Register */
20 #define PA_STATUS 0xb0000002 /* Switch Status Register */
21 #define PA_SHUTDOWN 0xb0000003 /* Shutdown Control Register */
22 #define PA_PCIPME 0xb0000004 /* PCI PME Status Register */
23 #define PA_IMASK 0xb0000005 /* Interrupt Mask Register */
25 #define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */
27 #define PA_PIDE_OFFSET 0x40 /* CF IDE Offset */
28 #define PA_SIDE_OFFSET 0x40 /* HDD IDE Offset */
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dfsl,imxrt1050.yaml72 reg = <0x401f8000 0x4000>;
76 <0x0EC 0x2DC 0x000 0x2 0x0 0xf1>,
77 <0x0F0 0x2E0 0x000 0x2 0x0 0xf1>;
/Linux-v6.1/arch/arm/boot/dts/
Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
Ddm814x-clocks.dtsi12 reg = <0x40 0x40>;
24 reg = <0x80 0x30>;
35 reg = <0xb0 0x30>;
46 reg = <0xe0 0x30>;
57 reg = <0x110 0x30>;
68 reg = <0x140 0x30>;
79 reg = <0x170 0x30>;
90 reg = <0x1a0 0x30>;
101 reg = <0x1d0 0x30>;
112 reg = <0x200 0x30>;
[all …]
Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
/Linux-v6.1/drivers/clk/mediatek/
Dclk-mt8186-mcu.c39 MUX(CLK_MCU_ARMPLL_LL_SEL, "mcu_armpll_ll_sel", mcu_armpll_ll_parents, 0x2A0, 9, 2),
41 MUX(CLK_MCU_ARMPLL_BL_SEL, "mcu_armpll_bl_sel", mcu_armpll_bl_parents, 0x2A4, 9, 2),
43 MUX(CLK_MCU_ARMPLL_BUS_SEL, "mcu_armpll_bus_sel", mcu_armpll_bus_parents, 0x2E0, 9, 2),
62 base = devm_platform_ioremap_resource(pdev, 0); in clk_mt8186_mcu_probe()
97 return 0; in clk_mt8186_mcu_remove()
/Linux-v6.1/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
[all …]
/Linux-v6.1/arch/sh/include/mach-se/mach/
Dse.h16 #define PA_ROM 0x00000000 /* EPROM */
17 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
18 #define PA_FROM 0x01000000 /* EPROM */
19 #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
20 #define PA_EXT1 0x04000000
21 #define PA_EXT1_SIZE 0x04000000
22 #define PA_EXT2 0x08000000
23 #define PA_EXT2_SIZE 0x04000000
24 #define PA_SDRAM 0x0c000000
25 #define PA_SDRAM_SIZE 0x04000000
[all …]
/Linux-v6.1/drivers/clk/meson/
Daxg.h19 #define HHI_GP0_PLL_CNTL 0x40
20 #define HHI_GP0_PLL_CNTL2 0x44
21 #define HHI_GP0_PLL_CNTL3 0x48
22 #define HHI_GP0_PLL_CNTL4 0x4c
23 #define HHI_GP0_PLL_CNTL5 0x50
24 #define HHI_GP0_PLL_STS 0x54
25 #define HHI_GP0_PLL_CNTL1 0x58
26 #define HHI_HIFI_PLL_CNTL 0x80
27 #define HHI_HIFI_PLL_CNTL2 0x84
28 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
/Linux-v6.1/drivers/memory/tegra/
Dtegra234.c19 .override = 0x2c0,
20 .security = 0x2c4,
29 .override = 0x2c8,
30 .security = 0x2cc,
39 .override = 0x2d0,
40 .security = 0x2d4,
49 .override = 0x2d8,
50 .security = 0x2dc,
59 .override = 0x2e0,
60 .security = 0x2e4,
[all …]
/Linux-v6.1/drivers/staging/rtl8712/
Drtl8712_spec.h17 #define RTL8712_IOBASE_TXPKT 0x10200000 /*IOBASE_TXPKT*/
18 #define RTL8712_IOBASE_RXPKT 0x10210000 /*IOBASE_RXPKT*/
19 #define RTL8712_IOBASE_RXCMD 0x10220000 /*IOBASE_RXCMD*/
20 #define RTL8712_IOBASE_TXSTATUS 0x10230000 /*IOBASE_TXSTATUS*/
21 #define RTL8712_IOBASE_RXSTATUS 0x10240000 /*IOBASE_RXSTATUS*/
22 #define RTL8712_IOBASE_IOREG 0x10250000 /*IOBASE_IOREG ADDR*/
23 #define RTL8712_IOBASE_SCHEDULER 0x10260000 /*IOBASE_SCHEDULE*/
25 #define RTL8712_IOBASE_TRXDMA 0x10270000 /*IOBASE_TRXDMA*/
26 #define RTL8712_IOBASE_TXLLT 0x10280000 /*IOBASE_TXLLT*/
27 #define RTL8712_IOBASE_WMAC 0x10290000 /*IOBASE_WMAC*/
[all …]
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
/Linux-v6.1/arch/sh/include/mach-sdk7786/mach/
Dfpga.h9 #define SRSTR 0x000
10 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */
12 #define INTASR 0x010
13 #define INTAMR 0x020
14 #define MODSWR 0x030
15 #define INTTESTR 0x040
16 #define SYSSR 0x050
17 #define NRGPR 0x060
19 #define NMISR 0x070
20 #define NMISR_MAN_NMI BIT(0)
[all …]
/Linux-v6.1/arch/powerpc/kernel/
Dexceptions-64e.S39 #define SPECIAL_EXC_SRR0 0
83 lwz r12,0(r11)
119 li r10,0
144 lwz r12,0(r11)
163 PPC_TLBILX_ALL(0,R0)
199 stdcx. r0,0,r1 /* to clear the reservation */
226 REST_GPR(0, r1)
260 cmpdi cr1,r1,0; /* check if SP makes sense */ \
365 SAVE_GPR(0, r1); /* save r0 in stackframe */ \
382 ZEROIZE_GPR(0); \
[all …]
/Linux-v6.1/Documentation/networking/
Darcnet.rst220 insmod com20020.o io=0x2e0 device=eth1
250 LILO: linux com20020=0x2e0 com20020=0x380 com90io=0x260
256 insmod -o arc1 com20020 io=0x2e0
561 arcnet.c). arcdump assumes your card is at 0xD0000. If it isn't, edit the
564 Buffers 0 and 1 are used for receiving, and Buffers 2 and 3 are for sending.
568 the buffers are cleared to a constant value of 0x42 every time the card is
571 buffer will be cleared to 0x42 as well. This is to make it easier to figure
/Linux-v6.1/drivers/video/fbdev/via/
Daccel.h14 #define MMIO_VGABASE 0x8000
15 #define MMIO_CR_READ (MMIO_VGABASE + 0x3D4)
16 #define MMIO_CR_WRITE (MMIO_VGABASE + 0x3D5)
17 #define MMIO_SR_READ (MMIO_VGABASE + 0x3C4)
18 #define MMIO_SR_WRITE (MMIO_VGABASE + 0x3C5)
21 #define HW_Cursor_ON 0
27 #define VIA_MMIO_BLTBASE 0x200000
28 #define VIA_MMIO_BLTSIZE 0x200000
31 #define VIA_REG_GECMD 0x000
32 #define VIA_REG_GEMODE 0x004
[all …]
/Linux-v6.1/drivers/fsi/
Dfsi-master.h23 #define FSI_MMODE 0x0 /* R/W: mode */
24 #define FSI_MDLYR 0x4 /* R/W: delay */
25 #define FSI_MCRSP 0x8 /* R/W: clock rate */
26 #define FSI_MENP0 0x10 /* R/W: enable */
27 #define FSI_MLEVP0 0x18 /* R: plug detect */
28 #define FSI_MSENP0 0x18 /* S: Set enable */
29 #define FSI_MCENP0 0x20 /* C: Clear enable */
30 #define FSI_MAEB 0x70 /* R: Error address */
31 #define FSI_MVER 0x74 /* R: master version/type */
32 #define FSI_MSTAP0 0xd0 /* R: Port status */
[all …]
/Linux-v6.1/arch/sh/boards/mach-microdev/
Dirq.c23 { 0, 0, "unused" }, /* IRQ #0 IRL=15 0x200 */
24 { MICRODEV_FPGA_IRQ_KEYBOARD, 1, "keyboard" }, /* IRQ #1 IRL=14 0x220 */
25 { MICRODEV_FPGA_IRQ_SERIAL1, 1, "Serial #1"}, /* IRQ #2 IRL=13 0x240 */
26 { MICRODEV_FPGA_IRQ_ETHERNET, 1, "Ethernet" }, /* IRQ #3 IRL=12 0x260 */
27 { MICRODEV_FPGA_IRQ_SERIAL2, 0, "Serial #2"}, /* IRQ #4 IRL=11 0x280 */
28 { 0, 0, "unused" }, /* IRQ #5 IRL=10 0x2a0 */
29 { 0, 0, "unused" }, /* IRQ #6 IRL=9 0x2c0 */
30 { MICRODEV_FPGA_IRQ_USB_HC, 1, "USB" }, /* IRQ #7 IRL=8 0x2e0 */
31 { MICRODEV_IRQ_PCI_INTA, 1, "PCI INTA" }, /* IRQ #8 IRL=7 0x300 */
32 { MICRODEV_IRQ_PCI_INTB, 1, "PCI INTB" }, /* IRQ #9 IRL=6 0x320 */
[all …]
/Linux-v6.1/drivers/media/usb/go7007/
Ds2250-board.c26 #define TLV320_ADDRESS 0x34
27 #define VPX322_ADDR_ANALOGCONTROL1 0x02
28 #define VPX322_ADDR_BRIGHTNESS0 0x0127
29 #define VPX322_ADDR_BRIGHTNESS1 0x0131
30 #define VPX322_ADDR_CONTRAST0 0x0128
31 #define VPX322_ADDR_CONTRAST1 0x0132
32 #define VPX322_ADDR_HUE 0x00dc
33 #define VPX322_ADDR_SAT 0x0030
50 0x1e, 0x00,
51 0x00, 0x17,
[all …]
/Linux-v6.1/drivers/phy/qualcomm/
Dphy-qcom-qmp-qserdes-txrx-v5_5nm.h10 #define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_5NM_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_5NM_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V5_5NM_TX_LANE_MODE_3 0x80
15 #define QSERDES_V5_5NM_TX_BIST_MODE_LANENO 0x00
16 #define QSERDES_V5_5NM_TX_BIST_INVERT 0x04
17 #define QSERDES_V5_5NM_TX_CLKBUF_ENABLE 0x08
18 #define QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL 0x0c
19 #define QSERDES_V5_5NM_TX_TX_IDLE_LVL_LARGE_AMP 0x10
[all …]

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