Lines Matching +full:0 +full:x2e0
39 #define SPECIAL_EXC_SRR0 0
83 lwz r12,0(r11)
119 li r10,0
144 lwz r12,0(r11)
163 PPC_TLBILX_ALL(0,R0)
199 stdcx. r0,0,r1 /* to clear the reservation */
226 REST_GPR(0, r1)
260 cmpdi cr1,r1,0; /* check if SP makes sense */ \
365 SAVE_GPR(0, r1); /* save r0 in stackframe */ \
382 ZEROIZE_GPR(0); \
390 std r9,0(r1); /* store stack frame back link */ \
446 rlwinm r7,r10,0,~_TLF_NAPPING; \
467 .balign 0x1000
470 EXCEPTION_STUB(0x000, machine_check)
471 EXCEPTION_STUB(0x020, critical_input) /* 0x0100 */
472 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
473 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */
474 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */
475 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */
476 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */
477 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */
478 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */
479 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */
480 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */
481 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */
482 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */
483 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
484 EXCEPTION_STUB(0x1c0, data_tlb_miss)
485 EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
486 EXCEPTION_STUB(0x200, altivec_unavailable)
487 EXCEPTION_STUB(0x220, altivec_assist)
488 EXCEPTION_STUB(0x260, perfmon)
489 EXCEPTION_STUB(0x280, doorbell)
490 EXCEPTION_STUB(0x2a0, doorbell_crit)
491 EXCEPTION_STUB(0x2c0, guest_doorbell)
492 EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
493 EXCEPTION_STUB(0x300, hypercall)
494 EXCEPTION_STUB(0x320, ehpriv)
495 EXCEPTION_STUB(0x340, lrat_error)
502 CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
504 EXCEPTION_COMMON_CRIT(0x100)
513 MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK,
515 EXCEPTION_COMMON_MC(0x000)
524 NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE,
532 EXCEPTION_COMMON(0x300)
537 NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE,
539 li r15,0
545 EXCEPTION_COMMON(0x400)
549 MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
554 NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT,
562 EXCEPTION_COMMON(0x600)
567 NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
572 EXCEPTION_COMMON(0x700)
580 NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
583 EXCEPTION_COMMON(0x800)
595 NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL,
598 EXCEPTION_COMMON(0x200)
615 NORMAL_EXCEPTION_PROLOG(0x220,
618 EXCEPTION_COMMON(0x220)
632 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
636 MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
641 CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
643 EXCEPTION_COMMON_CRIT(0x9f0)
664 NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
666 EXCEPTION_COMMON(0xf20)
673 CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
706 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */
733 EXCEPTION_COMMON_CRIT(0xd00)
744 DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
777 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
804 EXCEPTION_COMMON_DBG(0xd08)
811 NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
813 EXCEPTION_COMMON(0x260)
827 MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
832 CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
834 EXCEPTION_COMMON_CRIT(0x2a0)
846 GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL,
848 EXCEPTION_COMMON(0x2c0)
855 CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
857 EXCEPTION_COMMON_CRIT(0x2e0)
866 NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
868 EXCEPTION_COMMON(0x310)
875 NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
877 EXCEPTION_COMMON(0x320)
884 NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR,
886 EXCEPTION_COMMON(0x340)
903 ld r11,0(r14)
915 li r11,0
945 cmpdi r11,0
966 masked_interrupt_book3e PACA_IRQ_DEC 0
970 masked_interrupt_book3e PACA_IRQ_DEC 0
974 masked_interrupt_book3e PACA_IRQ_DBELL 0
977 * This is called from 0x300 and 0x400 handlers after the prologs with
987 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
1003 BAD_STACK_TRAMPOLINE(0x000)
1004 BAD_STACK_TRAMPOLINE(0x100)
1005 BAD_STACK_TRAMPOLINE(0x200)
1006 BAD_STACK_TRAMPOLINE(0x220)
1007 BAD_STACK_TRAMPOLINE(0x260)
1008 BAD_STACK_TRAMPOLINE(0x280)
1009 BAD_STACK_TRAMPOLINE(0x2a0)
1010 BAD_STACK_TRAMPOLINE(0x2c0)
1011 BAD_STACK_TRAMPOLINE(0x2e0)
1012 BAD_STACK_TRAMPOLINE(0x300)
1013 BAD_STACK_TRAMPOLINE(0x310)
1014 BAD_STACK_TRAMPOLINE(0x320)
1015 BAD_STACK_TRAMPOLINE(0x340)
1016 BAD_STACK_TRAMPOLINE(0x400)
1017 BAD_STACK_TRAMPOLINE(0x500)
1018 BAD_STACK_TRAMPOLINE(0x600)
1019 BAD_STACK_TRAMPOLINE(0x700)
1020 BAD_STACK_TRAMPOLINE(0x800)
1021 BAD_STACK_TRAMPOLINE(0x900)
1022 BAD_STACK_TRAMPOLINE(0x980)
1023 BAD_STACK_TRAMPOLINE(0x9f0)
1024 BAD_STACK_TRAMPOLINE(0xa00)
1025 BAD_STACK_TRAMPOLINE(0xb00)
1026 BAD_STACK_TRAMPOLINE(0xc00)
1027 BAD_STACK_TRAMPOLINE(0xd00)
1028 BAD_STACK_TRAMPOLINE(0xd08)
1029 BAD_STACK_TRAMPOLINE(0xe00)
1030 BAD_STACK_TRAMPOLINE(0xf00)
1031 BAD_STACK_TRAMPOLINE(0xf20)
1049 SAVE_GPR(0, r1); /* save r0 in stackframe */ \
1068 std r11,0(r1)
1070 std r12,0(r11)
1086 lis r3,MAS0_TLBSEL(0)@h
1121 tlbsx 0,r6 /* search MSR[IS], SPID=PID */
1138 li r6,0 /* Set Entry counter to 0 */
1144 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
1155 PPC_TLBILX_ALL(0,R0)
1164 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
1165 addi r7,r7,0x1
1195 li r6,0
1208 rlwinm r6,r6,0,2,31 /* clear IPROT and VALID */
1214 /* 6. Setup KERNELBASE mapping in TLB[0]
1220 rlwinm r3,r3,0,16,3 /* clear ESEL */
1229 rlwinm r5,r5,0,0,25
1233 rlwinm r5,r5,0,0,25
1250 rfi /* start execution out of TLB1[0] entry */
1260 rlwinm r5,r5,0,2,31 /* clear IPROT and VALID */
1272 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
1301 li r3,0
1326 li r5,0
1328 tlbsx 0,r3
1330 rlwinm r9,r4,0,TLBnCFG_N_ENTRY
1331 rlwinm r10,r4,8,0xff
1337 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
1340 rldicr r6,r6,0,51 /* Extract EPN */
1343 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */
1345 rlwinm r8,r7,16,0xfff /* Extract ESEL */
1369 PPC_TLBILX(0,0,R0)
1383 * Main entry (boot CPU, thread 0)
1391 * - Kernel loaded at 0 physical
1392 * - A good lump of memory mapped 0:0 by UTLB entry 0
1393 * - MSR:IS & MSR:DS set to 0
1404 * and always use AS 0, so we just set it up to match our link
1405 * address and never use 0 based addresses.
1424 * This is entered for thread 0 of a secondary core, all other threads
1440 cmplwi r4,0
1461 * 1:1 mapping at 0, so we don't bother doing a complicated check
1470 cmpdi cr0,r28,0
1496 wrteei 0
1499 li r3,0
1507 SET_IVOR(0, 0x020) /* Critical Input */
1508 SET_IVOR(1, 0x000) /* Machine Check */
1509 SET_IVOR(2, 0x060) /* Data Storage */
1510 SET_IVOR(3, 0x080) /* Instruction Storage */
1511 SET_IVOR(4, 0x0a0) /* External Input */
1512 SET_IVOR(5, 0x0c0) /* Alignment */
1513 SET_IVOR(6, 0x0e0) /* Program */
1514 SET_IVOR(7, 0x100) /* FP Unavailable */
1515 SET_IVOR(8, 0x120) /* System Call */
1516 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
1517 SET_IVOR(10, 0x160) /* Decrementer */
1518 SET_IVOR(11, 0x180) /* Fixed Interval Timer */
1519 SET_IVOR(12, 0x1a0) /* Watchdog Timer */
1520 SET_IVOR(13, 0x1c0) /* Data TLB Error */
1521 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1522 SET_IVOR(15, 0x040) /* Debug */
1529 SET_IVOR(32, 0x200) /* AltiVec Unavailable */
1530 SET_IVOR(33, 0x220) /* AltiVec Assist */
1534 SET_IVOR(35, 0x260) /* Performance Monitor */
1538 SET_IVOR(36, 0x280) /* Processor Doorbell */
1539 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1543 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1544 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
1545 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1546 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1550 SET_IVOR(42, 0x340) /* LRAT Error */