Lines Matching +full:0 +full:x2e0
23 #define FSI_MMODE 0x0 /* R/W: mode */
24 #define FSI_MDLYR 0x4 /* R/W: delay */
25 #define FSI_MCRSP 0x8 /* R/W: clock rate */
26 #define FSI_MENP0 0x10 /* R/W: enable */
27 #define FSI_MLEVP0 0x18 /* R: plug detect */
28 #define FSI_MSENP0 0x18 /* S: Set enable */
29 #define FSI_MCENP0 0x20 /* C: Clear enable */
30 #define FSI_MAEB 0x70 /* R: Error address */
31 #define FSI_MVER 0x74 /* R: master version/type */
32 #define FSI_MSTAP0 0xd0 /* R: Port status */
33 #define FSI_MRESP0 0xd0 /* W: Port reset */
34 #define FSI_MESRB0 0x1d0 /* R: Master error status */
35 #define FSI_MRESB0 0x1d0 /* W: Reset bridge */
36 #define FSI_MSCSB0 0x1d4 /* R: Master sub command stack */
37 #define FSI_MATRB0 0x1d8 /* R: Master address trace */
38 #define FSI_MDTRB0 0x1dc /* R: Master data trace */
39 #define FSI_MECTRL 0x2e0 /* W: Error control */
42 #define FSI_MMODE_EIP 0x80000000 /* Enable interrupt polling */
43 #define FSI_MMODE_ECRC 0x40000000 /* Enable error recovery */
44 #define FSI_MMODE_RELA 0x20000000 /* Enable relative address commands */
45 #define FSI_MMODE_EPC 0x10000000 /* Enable parity checking */
46 #define FSI_MMODE_P8_TO_LSB 0x00000010 /* Timeout value LSB */
47 /* MSB=1, LSB=0 is 0.8 ms */
48 /* MSB=0, LSB=1 is 0.9 ms */
49 #define FSI_MMODE_CRS0SHFT 18 /* Clk rate selection 0 shift */
50 #define FSI_MMODE_CRS0MASK 0x3ff /* Clk rate selection 0 mask */
52 #define FSI_MMODE_CRS1MASK 0x3ff /* Clk rate selection 1 mask */
55 #define FSI_MRESB_RST_GEN 0x80000000 /* General reset */
56 #define FSI_MRESB_RST_ERR 0x40000000 /* Error Reset */
59 #define FSI_MRESP_RST_ALL_MASTER 0x20000000 /* Reset all FSI masters */
60 #define FSI_MRESP_RST_ALL_LINK 0x10000000 /* Reset all FSI port contr. */
61 #define FSI_MRESP_RST_MCR 0x08000000 /* Reset FSI master reg. */
62 #define FSI_MRESP_RST_PYE 0x04000000 /* Reset FSI parity error */
63 #define FSI_MRESP_RST_ALL 0xfc000000 /* Reset any error */
66 #define FSI_MECTRL_EOAE 0x8000 /* Enable machine check when */
67 /* master 0 in error */
68 #define FSI_MECTRL_P8_AUTO_TERM 0x4000 /* Auto terminate */
70 #define FSI_HUB_LINK_OFFSET 0x80000
71 #define FSI_HUB_LINK_SIZE 0x80000
96 #define FSI_CMD_DPOLL 0x2
97 #define FSI_CMD_EPOLL 0x3
98 #define FSI_CMD_TERM 0x3f
99 #define FSI_CMD_ABS_AR 0x4
100 #define FSI_CMD_REL_AR 0x5
101 #define FSI_CMD_SAME_AR 0x3 /* but only a 2-bit opcode... */
104 #define FSI_RESP_ACK 0 /* Success */
113 #define FSI_MASTER_FLAG_SWCLOCK 0x1