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/Linux-v5.10/Documentation/devicetree/bindings/riscv/
Dsifive-l2-cache.yaml91 reg = <0x2010000 0x1000>;
/Linux-v5.10/drivers/media/dvb-frontends/
Ddrxd_map_firm.h18 #define HI_COMM_EXEC__A 0x400000
19 #define HI_COMM_MB__A 0x400002
20 #define HI_CT_REG_COMM_STATE__A 0x410001
21 #define HI_RA_RAM_SRV_RES__A 0x420031
22 #define HI_RA_RAM_SRV_CMD__A 0x420032
23 #define HI_RA_RAM_SRV_CMD_RESET 0x2
24 #define HI_RA_RAM_SRV_CMD_CONFIG 0x3
25 #define HI_RA_RAM_SRV_CMD_EXECUTE 0x6
26 #define HI_RA_RAM_SRV_RST_KEY__A 0x420033
27 #define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973
[all …]
/Linux-v5.10/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
31 reg = <0>;
144 compatible = "sifive,plic-1.0.0";
145 reg = <0x0 0xc000000 0x0 0x4000000>;
149 &cpu0_intc 0xffffffff
150 &cpu1_intc 0xffffffff &cpu1_intc 9
151 &cpu2_intc 0xffffffff &cpu2_intc 9
152 &cpu3_intc 0xffffffff &cpu3_intc 9
153 &cpu4_intc 0xffffffff &cpu4_intc 9>;
[all …]
/Linux-v5.10/arch/arm64/boot/dts/mediatek/
Dmt8516.dtsi21 cluster0_opp: opp-table-0 {
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0>;
66 reg = <0x1>;
79 reg = <0x2>;
92 reg = <0x3>;
105 CPU_SLEEP_0_0: cpu-sleep-0-0 {
110 arm,psci-suspend-param = <0x0010000>;
113 CLUSTER_SLEEP_0: cluster-sleep-0 {
[all …]
/Linux-v5.10/arch/arm64/boot/dts/ti/
Dk3-j7200-main.dtsi11 reg = <0x00 0x70000000 0x00 0x100000>;
14 ranges = <0x00 0x00 0x70000000 0x100000>;
16 atf-sram@0 {
17 reg = <0x00 0x20000>;
23 reg = <0x00 0x00100000 0x00 0x1c000>;
26 ranges = <0x00 0x00 0x00100000 0x1c000>;
31 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
32 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
38 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
49 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
[all …]
Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>; /* GICR */
47 reg = <0x00 0x01820000 0x00 0x10000>;
48 socionext,synquacer-pre-its = <0x1000000 0x400000>;
[all …]
Dk3-j721e-main.dtsi14 reg = <0x0 0x70000000 0x0 0x800000>;
17 ranges = <0x0 0x0 0x70000000 0x800000>;
19 atf-sram@0 {
20 reg = <0x0 0x20000>;
26 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
29 ranges = <0x0 0x0 0x00100000 0x1c000>;
33 reg = <0x00004070 0x4>;
36 ranges = <0x4070 0x4070 0x4>;
41 reg = <0x00004074 0x4>;
44 ranges = <0x4074 0x4074 0x4>;
[all …]
/Linux-v5.10/arch/arm64/boot/dts/freescale/
Dfsl-ls1088a.dtsi26 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0x0>;
33 clocks = <&clockgen 1 0>;
41 reg = <0x1>;
42 clocks = <&clockgen 1 0>;
50 reg = <0x2>;
51 clocks = <&clockgen 1 0>;
59 reg = <0x3>;
60 clocks = <&clockgen 1 0>;
[all …]
Dfsl-ls208xa.dtsi32 #size-cells = <0>;
37 reg = <0x00000000 0x80000000 0 0x80000000>;
43 #clock-cells = <0>;
50 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
51 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
52 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
53 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
54 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
60 interrupts = <1 9 0x4>;
65 reg = <0x0 0x6020000 0 0x20000>;
[all …]
Dfsl-ls1028a.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
31 reg = <0x0>;
33 clocks = <&clockgen 1 0>;
42 reg = <0x1>;
44 clocks = <&clockgen 1 0>;
65 arm,psci-suspend-param = <0x0>;
74 #clock-cells = <0>;
81 #clock-cells = <0>;
88 reg = <0x0 0xf1f0000 0x0 0xffff>;
[all …]
Dfsl-lx2160a.dtsi11 /memreserve/ 0x80000000 0x00010000;
25 #size-cells = <0>;
28 cpu0: cpu@0 {
32 reg = <0x0>;
33 clocks = <&clockgen 1 0>;
34 d-cache-size = <0x8000>;
37 i-cache-size = <0xC000>;
49 reg = <0x1>;
50 clocks = <&clockgen 1 0>;
51 d-cache-size = <0x8000>;
[all …]
/Linux-v5.10/drivers/media/dvb-frontends/drx39xyj/
Ddrxj_map.h37 * Generated by: IDF:x 1.3.0
56 #define ATV_COMM_EXEC__A 0xC00000
58 #define ATV_COMM_EXEC__M 0x3
59 #define ATV_COMM_EXEC__PRE 0x0
60 #define ATV_COMM_EXEC_STOP 0x0
61 #define ATV_COMM_EXEC_ACTIVE 0x1
62 #define ATV_COMM_EXEC_HOLD 0x2
64 #define ATV_COMM_STATE__A 0xC00001
66 #define ATV_COMM_STATE__M 0xFFFF
67 #define ATV_COMM_STATE__PRE 0x0
[all …]