Lines Matching +full:0 +full:x2010000
12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>; /* GICR */
47 reg = <0x00 0x01820000 0x00 0x10000>;
48 socionext,synquacer-pre-its = <0x1000000 0x400000>;
56 reg = <0x0 0x900000 0x0 0x2000>;
66 mux-controls = <&serdes_mux 0>;
71 reg = <0x0 0x910000 0x0 0x2000>;
86 reg = <0x00 0x02800000 0x00 0x100>;
97 reg = <0x00 0x02810000 0x00 0x100>;
107 reg = <0x00 0x02820000 0x00 0x100>;
117 reg = <0x0 0x4e00000 0x0 0x1200>;
121 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
124 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
125 <&main_udmap 0x4001>;
131 reg = <0x0 0x4e10000 0x0 0x7d>;
139 reg = <0x0 0x11c000 0x0 0x2e4>;
142 pinctrl-single,function-mask = <0xffffffff>;
147 reg = <0x0 0x11c2e8 0x0 0x24>;
150 pinctrl-single,function-mask = <0xffffffff>;
155 reg = <0x0 0x2000000 0x0 0x100>;
158 #size-cells = <0>;
166 reg = <0x0 0x2010000 0x0 0x100>;
169 #size-cells = <0>;
177 reg = <0x0 0x2020000 0x0 0x100>;
180 #size-cells = <0>;
188 reg = <0x0 0x2030000 0x0 0x100>;
191 #size-cells = <0>;
200 reg = <0x0 0x03100000 0x0 0x60>;
202 clocks = <&k3_clks 39 0>;
208 reg = <0x0 0x2100000 0x0 0x400>;
213 #size-cells = <0>;
214 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
220 reg = <0x0 0x2110000 0x0 0x400>;
225 #size-cells = <0>;
232 reg = <0x0 0x2120000 0x0 0x400>;
237 #size-cells = <0>;
242 reg = <0x0 0x2130000 0x0 0x400>;
247 #size-cells = <0>;
252 reg = <0x0 0x2140000 0x0 0x400>;
257 #size-cells = <0>;
262 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
264 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
269 ti,otap-del-sel-legacy = <0x0>;
270 ti,otap-del-sel-mmc-hs = <0x0>;
271 ti,otap-del-sel-sd-hs = <0x0>;
272 ti,otap-del-sel-sdr12 = <0x0>;
273 ti,otap-del-sel-sdr25 = <0x0>;
274 ti,otap-del-sel-sdr50 = <0x8>;
275 ti,otap-del-sel-sdr104 = <0x7>;
276 ti,otap-del-sel-ddr50 = <0x5>;
277 ti,otap-del-sel-ddr52 = <0x5>;
278 ti,otap-del-sel-hs200 = <0x5>;
279 ti,otap-del-sel-hs400 = <0x0>;
280 ti,trm-icp = <0x8>;
286 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
288 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
291 ti,otap-del-sel-legacy = <0x0>;
292 ti,otap-del-sel-mmc-hs = <0x0>;
293 ti,otap-del-sel-sd-hs = <0x0>;
294 ti,otap-del-sel-sdr12 = <0x0>;
295 ti,otap-del-sel-sdr25 = <0x0>;
296 ti,otap-del-sel-sdr50 = <0x8>;
297 ti,otap-del-sel-sdr104 = <0x7>;
298 ti,otap-del-sel-ddr50 = <0x4>;
299 ti,otap-del-sel-ddr52 = <0x4>;
300 ti,otap-del-sel-hs200 = <0x7>;
301 ti,clkbuf-sel = <0x7>;
302 ti,otap-del-sel = <0x2>;
303 ti,trm-icp = <0x8>;
310 reg = <0 0x00100000 0 0x1c000>;
313 ranges = <0x0 0x0 0x00100000 0x1c000>;
317 reg = <0x00004060 0x4>;
322 reg = <0x00004070 0x4>;
327 reg = <0x00000210 0x4>;
332 reg = <0x00004080 0x4>;
337 reg = <0x00004090 0x4>;
343 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
344 <0x4090 0x3>; /* SERDES1 lane select */
349 reg = <0x0000041e0 0x14>;
354 reg = <0x4140 0x18>;
361 reg = <0x0 0x4000000 0x0 0x4000>;
364 ranges = <0x0 0x0 0x4000000 0x20000>;
375 reg = <0x10000 0x10000>;
392 reg = <0x0 0x4100000 0x0 0x54>;
393 syscon-phy-power = <&scm_conf 0x4000>;
394 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
396 #phy-cells = <0>;
401 reg = <0x0 0x4020000 0x0 0x4000>;
404 ranges = <0x0 0x0 0x4020000 0x20000>;
414 reg = <0x10000 0x10000>;
430 reg = <0x0 0x4110000 0x0 0x54>;
431 syscon-phy-power = <&scm_conf 0x4020>;
432 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
434 #phy-cells = <0>;
445 ti,interrupt-ranges = <0 392 32>;
466 ti,interrupt-ranges = <0 64 64>,
472 reg = <0x0 0x33d00000 0x0 0x100000>;
478 ti,interrupt-ranges = <0 0 256>;
485 reg = <0x00 0x32c00000 0x00 0x100000>,
486 <0x00 0x32400000 0x00 0x100000>,
487 <0x00 0x32800000 0x00 0x100000>;
494 reg = <0x00 0x30e00000 0x00 0x1000>;
500 reg = <0x00 0x31f80000 0x00 0x200>;
509 reg = <0x00 0x31f81000 0x00 0x200>;
518 reg = <0x00 0x31f82000 0x00 0x200>;
527 reg = <0x00 0x31f83000 0x00 0x200>;
536 reg = <0x00 0x31f84000 0x00 0x200>;
545 reg = <0x00 0x31f85000 0x00 0x200>;
554 reg = <0x00 0x31f86000 0x00 0x200>;
563 reg = <0x00 0x31f87000 0x00 0x200>;
572 reg = <0x00 0x31f88000 0x00 0x200>;
581 reg = <0x00 0x31f89000 0x00 0x200>;
590 reg = <0x00 0x31f8a000 0x00 0x200>;
599 reg = <0x00 0x31f8b000 0x00 0x200>;
608 reg = <0x0 0x3c000000 0x0 0x400000>,
609 <0x0 0x38000000 0x0 0x400000>,
610 <0x0 0x31120000 0x0 0x100>,
611 <0x0 0x33000000 0x0 0x40000>;
614 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
623 reg = <0x0 0x31150000 0x0 0x100>,
624 <0x0 0x34000000 0x0 0x100000>,
625 <0x0 0x35000000 0x0 0x100000>;
634 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
635 <0xd>; /* TX_CHAN */
636 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
637 <0xa>; /* RX_CHAN */
638 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
643 reg = <0x0 0x310d0000 0x0 0x400>;
653 #clock-cells = <0>;
666 reg = <0x0 0x600000 0x0 0x100>;
674 ti,davinci-gpio-unbanked = <0>;
675 clocks = <&k3_clks 57 0>;
681 reg = <0x0 0x601000 0x0 0x100>;
689 ti,davinci-gpio-unbanked = <0>;
690 clocks = <&k3_clks 58 0>;
696 …reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0…
701 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
702 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
705 bus-range = <0x0 0xff>;
710 msi-map = <0x0 &gic_its 0x0 0x10000>;
715 …reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x…
728 …reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0…
733 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
734 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
737 bus-range = <0x0 0xff>;
742 msi-map = <0x0 &gic_its 0x10000 0x10000>;
747 …reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x…
760 reg = <0x0 0x02b00000 0x0 0x2000>,
761 <0x0 0x02b08000 0x0 0x1000>;
767 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
770 clocks = <&k3_clks 104 0>;
779 reg = <0x0 0x02b10000 0x0 0x2000>,
780 <0x0 0x02b18000 0x0 0x1000>;
786 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
789 clocks = <&k3_clks 105 0>;
798 reg = <0x0 0x02b20000 0x0 0x2000>,
799 <0x0 0x02b28000 0x0 0x1000>;
805 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
808 clocks = <&k3_clks 106 0>;
817 reg = <0x0 0x06f03000 0x0 0x400>,
818 <0x0 0x06f03800 0x0 0x40>;
822 ti,camerrx-control = <&scm_conf 0x40c0>;
824 clocks = <&k3_clks 2 0>;
829 #size-cells = <0>;
831 csi2_0: port@0 {
832 reg = <0>;
839 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
840 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
841 <0x0 0x04a06000 0x0 0x1000>, /* vid */
842 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
843 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
844 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
845 <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
872 #size-cells = <0>;
879 reg = <0x0 0x3000000 0x0 0x100>;
881 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
888 reg = <0x0 0x3010000 0x0 0x100>;
890 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
897 reg = <0x0 0x3020000 0x0 0x100>;
899 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
906 reg = <0x0 0x3030000 0x0 0x100>;
908 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
915 reg = <0x0 0x3040000 0x0 0x100>;
917 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
924 reg = <0x0 0x3050000 0x0 0x100>;
926 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;