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/Linux-v5.10/drivers/clk/st/
Dclkgen-pll.c26 #define C32_NDIV_MASK (0xff)
27 #define C32_IDF_MASK (0x7)
28 #define C32_ODF_MASK (0x3f)
29 #define C32_LDF_MASK (0x7f)
30 #define C32_CP_MASK (0x1f)
37 #define C28_NDIV_MASK (0xff)
38 #define C28_IDF_MASK (0x7)
39 #define C28_ODF_MASK (0x3f)
66 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
67 .pdn_ctrl = CLKGEN_FIELD(0x2a0, 0x1, 8),
[all …]
/Linux-v5.10/drivers/media/platform/coda/
Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/Linux-v5.10/drivers/phy/qualcomm/
Dphy-qcom-qmp.h10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/
Daspeed,ast2xxx-scu-ic.txt15 ranges = <0 0x1e6e2000 0x1a8>;
/Linux-v5.10/Documentation/devicetree/bindings/mfd/
Daspeed-scu.txt19 reg = <0x1e6e2000 0x1a8>;
/Linux-v5.10/drivers/tty/serial/8250/
D8250_fourport.c16 SERIAL8250_FOURPORT(0x1a0, 9),
17 SERIAL8250_FOURPORT(0x1a8, 9),
18 SERIAL8250_FOURPORT(0x1b0, 9),
19 SERIAL8250_FOURPORT(0x1b8, 9),
20 SERIAL8250_FOURPORT(0x2a0, 5),
21 SERIAL8250_FOURPORT(0x2a8, 5),
22 SERIAL8250_FOURPORT(0x2b0, 5),
23 SERIAL8250_FOURPORT(0x2b8, 5),
/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dg84.c34 if (nvkm_fuse_read(device->fuse, 0x1a8) == 1) in g84_temp_get()
35 return nvkm_rd32(device, 0x20400); in g84_temp_get()
46 if (nvkm_fuse_read(device->fuse, 0x1a8) == 1) { in g84_sensor_setup()
47 nvkm_mask(device, 0x20008, 0x80008000, 0x80000000); in g84_sensor_setup()
48 nvkm_mask(device, 0x2000c, 0x80000003, 0x00000000); in g84_sensor_setup()
63 /* enable RISING and FALLING IRQs for shutdown, THRS 0, 1, 2 and 4 */ in g84_therm_program_alarms()
64 nvkm_wr32(device, 0x20000, 0x000003ff); in g84_therm_program_alarms()
67 nvkm_wr32(device, 0x20484, sensor->thrs_shutdown.hysteresis); in g84_therm_program_alarms()
68 nvkm_wr32(device, 0x20480, sensor->thrs_shutdown.temp); in g84_therm_program_alarms()
71 nvkm_wr32(device, 0x204c4, sensor->thrs_fan_boost.temp); in g84_therm_program_alarms()
[all …]
/Linux-v5.10/arch/m68k/ifpsp060/
Dfplsp.doc87 fmovm.x &0x01,-(%sp) # pass operand on stack
88 bsr.l _060FPLSP_TOP+0x1a8 # branch to fsin routine
89 add.l &0xc,%sp # clear operand from stack
100 bsr.l _060FPLSP_TOP+0x168 # branch to frem routine
101 addq.l &0x8,%sp # clear operands from stack
132 0x000: _060LSP__facoss_
133 0x008: _060LSP__facosd_
134 0x010: _060LSP__facosx_
135 0x018: _060LSP__fasins_
136 0x020: _060LSP__fasind_
[all …]
/Linux-v5.10/arch/arm64/boot/dts/freescale/
Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
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Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/Linux-v5.10/drivers/usb/host/
Dehci-fsl.h9 #define FSL_SOC_USB_SBUSCFG 0x90
10 #define SBUSCFG_INCR8 0x02 /* INCR8, specified */
11 #define FSL_SOC_USB_ULPIVP 0x170
12 #define FSL_SOC_USB_PORTSC1 0x184
14 #define PORT_PTS_UTMI (0<<30)
18 #define FSL_SOC_USB_PORTSC2 0x188
19 #define FSL_SOC_USB_USBMODE 0x1a8
20 #define USBMODE_CM_MASK (3 << 0) /* controller mode mask */
21 #define USBMODE_CM_HOST (3 << 0) /* controller mode: host */
24 #define FSL_SOC_USB_USBGENCTRL 0x200
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/misc/
Daspeed-p2a-ctrl.txt40 reg = <0x1e6e2000 0x1a8>;
/Linux-v5.10/Documentation/devicetree/bindings/pinctrl/
Daspeed,ast2400-pinctrl.yaml63 reg = <0x1e6e2000 0x1a8>;
/Linux-v5.10/drivers/usb/gadget/udc/
Dfotg210.h14 /* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */
15 #define FOTG210_GMIR 0xC4
16 #define GMIR_INT_POLARITY 0x8 /*Active High*/
17 #define GMIR_MHC_INT 0x4
18 #define GMIR_MOTG_INT 0x2
19 #define GMIR_MDEV_INT 0x1
21 /* Device Main Control Register(0x100) */
22 #define FOTG210_DMCR 0x100
29 #define DMCR_CAP_RMWAKUP (1 << 0)
31 /* Device Address Register(0x104) */
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
Ddra72x-mmc-iodelay.dtsi45 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
46 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
47 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
48 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
49 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
50 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
56 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
57 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
58 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
59 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
/Linux-v5.10/drivers/gpu/drm/vc4/
Dvc4_hdmi_regs.h6 #define VC4_HDMI_PACKET_STRIDE 0x24
9 VC4_INVALID = 0,
146 VC4_HD_REG(HDMI_M_CTL, 0x000c),
147 VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
148 VC4_HD_REG(HDMI_MAI_THR, 0x0018),
149 VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
150 VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
151 VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
152 VC4_HD_REG(HDMI_VID_CTL, 0x0038),
153 VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
[all …]
/Linux-v5.10/drivers/thermal/ti-soc-thermal/
Domap5xxx-bandgap.h29 #define OMAP5430_FUSE_OPP_BGAP_GPU 0x0
30 #define OMAP5430_TEMP_SENSOR_GPU_OFFSET 0x150
31 #define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET 0x1A8
32 #define OMAP5430_BGAP_TSHUT_GPU_OFFSET 0x1B4
33 #define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET 0x1F8
34 #define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET 0x1FC
37 #define OMAP5430_FUSE_OPP_BGAP_MPU 0x4
38 #define OMAP5430_TEMP_SENSOR_MPU_OFFSET 0x14C
39 #define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET 0x1A4
40 #define OMAP5430_BGAP_TSHUT_MPU_OFFSET 0x1B0
[all …]
/Linux-v5.10/tools/perf/arch/powerpc/util/
Dbook3s_hcalls.h9 {0x4, "H_REMOVE"}, \
10 {0x8, "H_ENTER"}, \
11 {0xc, "H_READ"}, \
12 {0x10, "H_CLEAR_MOD"}, \
13 {0x14, "H_CLEAR_REF"}, \
14 {0x18, "H_PROTECT"}, \
15 {0x1c, "H_GET_TCE"}, \
16 {0x20, "H_PUT_TCE"}, \
17 {0x24, "H_SET_SPRG0"}, \
18 {0x28, "H_SET_DABR"}, \
[all …]
/Linux-v5.10/include/dt-bindings/clock/
Domap5.h8 #define OMAP5_CLKCTRL_OFFSET 0x20
12 #define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
15 #define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
18 #define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
19 #define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
20 #define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
21 #define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
22 #define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
23 #define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
24 #define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
[all …]
Ddra7.h8 #define DRA7_CLKCTRL_OFFSET 0x20
14 #define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
17 #define _DRA7_IPU_CLKCTRL_OFFSET 0x40
19 #define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50)
20 #define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58)
21 #define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60)
22 #define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68)
23 #define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70)
24 #define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78)
25 #define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80)
[all …]

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