26 #define C32_NDIV_MASK (0xff)
27 #define C32_IDF_MASK (0x7)
28 #define C32_ODF_MASK (0x3f)
29 #define C32_LDF_MASK (0x7f)
30 #define C32_CP_MASK (0x1f)
37 #define C28_NDIV_MASK (0xff)
38 #define C28_IDF_MASK (0x7)
39 #define C28_ODF_MASK (0x3f)
66 	.pdn_status	= CLKGEN_FIELD(0x2a0,	0x1,			8),
67 	.pdn_ctrl	= CLKGEN_FIELD(0x2a0,	0x1,			8),
68 	.locked_status	= CLKGEN_FIELD(0x2a0,	0x1,			24),
69 	.ndiv		= CLKGEN_FIELD(0x2a4,	C32_NDIV_MASK,		16),
70 	.idf		= CLKGEN_FIELD(0x2a4,	C32_IDF_MASK,		0x0),
72 	.odf		= { CLKGEN_FIELD(0x2b4, C32_ODF_MASK,		0) },
73 	.odf_gate	= { CLKGEN_FIELD(0x2b4, 0x1,			6) },
79 	.pdn_status	= CLKGEN_FIELD(0x2c8,	0x1,			8),
80 	.pdn_ctrl	= CLKGEN_FIELD(0x2c8,	0x1,			8),
81 	.locked_status	= CLKGEN_FIELD(0x2c8,	0x1,			24),
82 	.ndiv		= CLKGEN_FIELD(0x2cc,	C32_NDIV_MASK,		16),
83 	.idf		= CLKGEN_FIELD(0x2cc,	C32_IDF_MASK,		0x0),
85 	.odf		= { CLKGEN_FIELD(0x2dc, C32_ODF_MASK,		0) },
86 	.odf_gate	= { CLKGEN_FIELD(0x2dc, 0x1,			6) },
92 	.pdn_status	= CLKGEN_FIELD(0x1a8,	0x1,			0),
93 	.pdn_ctrl	= CLKGEN_FIELD(0x1a8,	0x1,			0),
94 	.locked_status	= CLKGEN_FIELD(0x87c,	0x1,			0),
95 	.ndiv		= CLKGEN_FIELD(0x1b0,	C32_NDIV_MASK,		0),
96 	.idf		= CLKGEN_FIELD(0x1a8,	C32_IDF_MASK,		25),
98 	.odf		= { CLKGEN_FIELD(0x1b0, C32_ODF_MASK,		8) },
99 	.odf_gate	= { CLKGEN_FIELD(0x1ac, 0x1,			28) },
101 	.cp		= CLKGEN_FIELD(0x1a8,	C32_CP_MASK,		1),
102 	.switch2pll	= CLKGEN_FIELD(0x1a4,	0x1,			1),
109 	.pdn_status	= CLKGEN_FIELD(0x1a8,	0x1,			0),
110 	.pdn_ctrl	= CLKGEN_FIELD(0x1a8,	0x1,			0),
111 	.locked_status	= CLKGEN_FIELD(0x87c,	0x1,			0),
112 	.ndiv		= CLKGEN_FIELD(0x1b0,	C28_NDIV_MASK,		0),
113 	.idf		= CLKGEN_FIELD(0x1a8,	C28_IDF_MASK,		25),
115 	.odf		= { CLKGEN_FIELD(0x1b0, C28_ODF_MASK,		8) },
116 	.odf_gate	= { CLKGEN_FIELD(0x1ac, 0x1,			28) },
118 	.switch2pll	= CLKGEN_FIELD(0x1a4,	0x1,			1),
186 	int ret = 0;  in __clkgen_pll_enable()
190 		return 0;  in __clkgen_pll_enable()
192 	CLKGEN_WRITE(pll, pdn_ctrl, 0);  in __clkgen_pll_enable()
195 			!!((reg >> field->shift) & field->mask),  0, 10000);  in __clkgen_pll_enable()
199 			CLKGEN_WRITE(pll, switch2pll, 0);  in __clkgen_pll_enable()
210 	unsigned long flags = 0;  in clkgen_pll_enable()
211 	int ret = 0;  in clkgen_pll_enable()
242 	unsigned long flags = 0;  in clkgen_pll_disable()
257 	unsigned long deviation = ~0;  in clk_pll3200c32_get_params()
293 	if (deviation == ~0) /* No solution found */  in clk_pll3200c32_get_params()
300 	return 0;  in clk_pll3200c32_get_params()
311 	return 0;  in clk_pll3200c32_get_rate()
319 	unsigned long rate = 0;  in recalc_stm_pll3200c32()
322 		return 0;  in recalc_stm_pll3200c32()
346 		return 0;  in round_rate_stm_pll3200c32()
362 	long hwrate = 0;  in set_rate_stm_pll3200c32()
363 	unsigned long flags = 0;  in set_rate_stm_pll3200c32()
371 	pr_debug("%s: %s new rate %ld [ndiv=0x%x] [idf=0x%x]\n",  in set_rate_stm_pll3200c32()
397 	return 0;  in set_rate_stm_pll3200c32()
419 	unsigned long deviation = ~0;  in clk_pll4600c28_get_params()
453 	if (deviation == ~0) /* No solution found */  in clk_pll4600c28_get_params()
456 	return 0;  in clk_pll4600c28_get_params()
467 	return 0;  in clk_pll4600c28_get_rate()
478 		return 0;  in recalc_stm_pll4600c28()
500 		return 0;  in round_rate_stm_pll4600c28()
517 	unsigned long flags = 0;  in set_rate_stm_pll4600c28()
530 	pr_debug("%s: %s new rate %ld [ndiv=0x%x] [idf=0x%x]\n",  in set_rate_stm_pll4600c28()
554 	return 0;  in set_rate_stm_pll4600c28()
631 	reg = of_iomap(pnode, 0);  in clkgen_get_register_base()
696 	unsigned long pll_flags = 0;  in clkgen_c32_pll_setup()
699 	parent_name = of_clk_get_parent_name(np, 0);  in clkgen_c32_pll_setup()
707 	of_clk_detect_critical(np, 0, &pll_flags);  in clkgen_c32_pll_setup()
729 	for (odf = 0; odf < num_odfs; odf++) {  in clkgen_c32_pll_setup()
732 		unsigned long odf_flags = 0;  in clkgen_c32_pll_setup()