Lines Matching +full:0 +full:x1a8
6 #define VC4_HDMI_PACKET_STRIDE 0x24
9 VC4_INVALID = 0,
146 VC4_HD_REG(HDMI_M_CTL, 0x000c),
147 VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
148 VC4_HD_REG(HDMI_MAI_THR, 0x0018),
149 VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
150 VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
151 VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
152 VC4_HD_REG(HDMI_VID_CTL, 0x0038),
153 VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
154 VC4_HD_REG(HDMI_CSC_12_11, 0x0044),
155 VC4_HD_REG(HDMI_CSC_14_13, 0x0048),
156 VC4_HD_REG(HDMI_CSC_22_21, 0x004c),
157 VC4_HD_REG(HDMI_CSC_24_23, 0x0050),
158 VC4_HD_REG(HDMI_CSC_32_31, 0x0054),
159 VC4_HD_REG(HDMI_CSC_34_33, 0x0058),
160 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0068),
162 VC4_HDMI_REG(HDMI_CORE_REV, 0x0000),
163 VC4_HDMI_REG(HDMI_SW_RESET_CONTROL, 0x0004),
164 VC4_HDMI_REG(HDMI_HOTPLUG_INT, 0x0008),
165 VC4_HDMI_REG(HDMI_HOTPLUG, 0x000c),
166 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x005c),
167 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0090),
168 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0094),
169 VC4_HDMI_REG(HDMI_MAI_FORMAT, 0x0098),
170 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x009c),
171 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x00a0),
172 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x00a4),
173 VC4_HDMI_REG(HDMI_CRP_CFG, 0x00a8),
174 VC4_HDMI_REG(HDMI_CTS_0, 0x00ac),
175 VC4_HDMI_REG(HDMI_CTS_1, 0x00b0),
176 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x00c0),
177 VC4_HDMI_REG(HDMI_HORZA, 0x00c4),
178 VC4_HDMI_REG(HDMI_HORZB, 0x00c8),
179 VC4_HDMI_REG(HDMI_VERTA0, 0x00cc),
180 VC4_HDMI_REG(HDMI_VERTB0, 0x00d0),
181 VC4_HDMI_REG(HDMI_VERTA1, 0x00d4),
182 VC4_HDMI_REG(HDMI_VERTB1, 0x00d8),
183 VC4_HDMI_REG(HDMI_CEC_CNTRL_1, 0x00e8),
184 VC4_HDMI_REG(HDMI_CEC_CNTRL_2, 0x00ec),
185 VC4_HDMI_REG(HDMI_CEC_CNTRL_3, 0x00f0),
186 VC4_HDMI_REG(HDMI_CEC_CNTRL_4, 0x00f4),
187 VC4_HDMI_REG(HDMI_CEC_CNTRL_5, 0x00f8),
188 VC4_HDMI_REG(HDMI_CEC_TX_DATA_1, 0x00fc),
189 VC4_HDMI_REG(HDMI_CEC_TX_DATA_2, 0x0100),
190 VC4_HDMI_REG(HDMI_CEC_TX_DATA_3, 0x0104),
191 VC4_HDMI_REG(HDMI_CEC_TX_DATA_4, 0x0108),
192 VC4_HDMI_REG(HDMI_CEC_RX_DATA_1, 0x010c),
193 VC4_HDMI_REG(HDMI_CEC_RX_DATA_2, 0x0110),
194 VC4_HDMI_REG(HDMI_CEC_RX_DATA_3, 0x0114),
195 VC4_HDMI_REG(HDMI_CEC_RX_DATA_4, 0x0118),
196 VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0),
197 VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4),
198 VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340),
199 VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348),
200 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c),
201 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x034c),
202 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354),
203 VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400),
207 VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
208 VC4_HD_REG(HDMI_MAI_CTL, 0x0010),
209 VC4_HD_REG(HDMI_MAI_THR, 0x0014),
210 VC4_HD_REG(HDMI_MAI_FMT, 0x0018),
211 VC4_HD_REG(HDMI_MAI_DATA, 0x001c),
212 VC4_HD_REG(HDMI_MAI_SMP, 0x0020),
213 VC4_HD_REG(HDMI_VID_CTL, 0x0044),
214 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060),
216 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
217 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
218 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
219 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
220 VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
221 VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
222 VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
223 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
224 VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
225 VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
226 VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
227 VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
228 VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
229 VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
230 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
231 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
232 VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
234 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
235 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
237 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
238 VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
239 VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
240 VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
241 VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
242 VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
243 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
244 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
245 VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
246 VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
247 VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
248 VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
249 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
250 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
251 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
253 VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
254 VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
255 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
257 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
259 VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
260 VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
261 VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
262 VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
263 VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
264 VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
265 VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
266 VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
267 VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
268 VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
269 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
270 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
271 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
273 VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
274 VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
275 VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
276 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
277 VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
278 VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
279 VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
283 VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
284 VC4_HD_REG(HDMI_MAI_CTL, 0x0030),
285 VC4_HD_REG(HDMI_MAI_THR, 0x0034),
286 VC4_HD_REG(HDMI_MAI_FMT, 0x0038),
287 VC4_HD_REG(HDMI_MAI_DATA, 0x003c),
288 VC4_HD_REG(HDMI_MAI_SMP, 0x0040),
289 VC4_HD_REG(HDMI_VID_CTL, 0x0048),
290 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064),
292 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
293 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
294 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
295 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
296 VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
297 VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
298 VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
299 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
300 VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
301 VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
302 VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
303 VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
304 VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
305 VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
306 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
307 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
308 VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
310 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
311 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
313 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
314 VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
315 VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
316 VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
317 VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
318 VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
319 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
320 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
321 VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
322 VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
323 VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
324 VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
325 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
326 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
327 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
329 VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
330 VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
331 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
333 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
335 VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
336 VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
337 VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
338 VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
339 VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
340 VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
341 VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
342 VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
343 VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
344 VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
345 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
346 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
347 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
349 VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
350 VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
351 VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
352 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
353 VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
354 VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
355 VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
404 return 0; in vc4_hdmi_read()
412 return 0; in vc4_hdmi_read()