Searched +full:0 +full:x1294 (Results 1 – 16 of 16) sorted by relevance
75 reg = <0x12800000 0x1294>;
162 reg = <0x10d20000 0x1000>;163 ranges = <0x0 0x10d20000 0x6000>;168 reg = <0x4000 0x1000>;173 reg = <0x5000 0x1000>;179 reg = <0x10010000 0x30000>;185 reg = <0x03810000 0x0C>;195 reg = <0x11000000 0x10000>;208 #size-cells = <0>;209 reg = <0x12200000 0x2000>;212 fifo-depth = <0x40>;[all …]
17 #define USB_VENDOR_ID_258A 0x258a18 #define USB_DEVICE_ID_258A_6A88 0x6a8820 #define USB_VENDOR_ID_3M 0x059621 #define USB_DEVICE_ID_3M1968 0x050022 #define USB_DEVICE_ID_3M2256 0x050223 #define USB_DEVICE_ID_3M3266 0x050625 #define USB_VENDOR_ID_A4TECH 0x09da26 #define USB_DEVICE_ID_A4TECH_WCP32PU 0x000627 #define USB_DEVICE_ID_A4TECH_X5_005D 0x000a28 #define USB_DEVICE_ID_A4TECH_RP_649 0x001a[all …]
15 #define ID_REV (0x00)16 #define ID_REV_ID_MASK_ (0xFFFF0000)17 #define ID_REV_ID_LAN7430_ (0x74300000)18 #define ID_REV_ID_LAN7431_ (0x74310000)20 (((id_rev) & 0xFFF00000) == 0x74300000)21 #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF)22 #define ID_REV_CHIP_REV_A0_ (0x00000000)23 #define ID_REV_CHIP_REV_B0_ (0x00000010)25 #define FPGA_REV (0x04)26 #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF)[all …]
48 #clock-cells = <0>;53 #size-cells = <0>;59 reg = <0x100>;71 reg = <0x101>;81 reg = <0x102>;91 reg = <0x103>;97 cpu4: cpu@0 {101 reg = <0x0>;113 reg = <0x1>;123 reg = <0x2>;[all …]
23 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");27 MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");33 } while (0)56 { .addr = state->i2c_addr >> 1, .flags = 0, .len = 2 }, in dib3000mc_read_word()64 return 0; in dib3000mc_read_word()66 b[0] = (reg >> 8) | 0x80; in dib3000mc_read_word()68 b[2] = 0; in dib3000mc_read_word()69 b[3] = 0; in dib3000mc_read_word()71 msg[0].buf = b; in dib3000mc_read_word()86 .addr = state->i2c_addr >> 1, .flags = 0, .len = 4 in dib3000mc_write_word()[all …]
51 #define OPTION_VENDOR_ID 0x0AF052 #define OPTION_PRODUCT_COLT 0x500053 #define OPTION_PRODUCT_RICOLA 0x600054 #define OPTION_PRODUCT_RICOLA_LIGHT 0x610055 #define OPTION_PRODUCT_RICOLA_QUAD 0x620056 #define OPTION_PRODUCT_RICOLA_QUAD_LIGHT 0x630057 #define OPTION_PRODUCT_RICOLA_NDIS 0x605058 #define OPTION_PRODUCT_RICOLA_NDIS_LIGHT 0x615059 #define OPTION_PRODUCT_RICOLA_NDIS_QUAD 0x625060 #define OPTION_PRODUCT_RICOLA_NDIS_QUAD_LIGHT 0x6350[all …]
24 …SQ_DEBUG_STS_GLOBAL 0x030925 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 026 …SQ_DEBUG_STS_GLOBAL2 0x031027 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 028 …SQ_DEBUG_STS_GLOBAL3 0x031129 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 032 // base address: 0x800033 …GRBM_CNTL 0x000034 …ne mmGRBM_CNTL_BASE_IDX 035 …GRBM_SKEW_CNTL 0x0001[all …]
24 …SQ_DEBUG_STS_GLOBAL 0x10A925 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 026 …SQ_DEBUG_STS_GLOBAL2 0x10B027 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 030 // base address: 0x498031 …SDMA0_DEC_START 0x000032 …ne mmSDMA0_DEC_START_BASE_IDX 033 …SDMA0_PG_CNTL 0x001634 …ne mmSDMA0_PG_CNTL_BASE_IDX 035 …SDMA0_PG_CTX_LO 0x0017[all …]
25 …SQ_DEBUG_STS_GLOBAL 0x10A926 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 027 …SQ_DEBUG_STS_GLOBAL2 0x10B028 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 031 // base address: 0x498032 …SDMA0_DEC_START 0x000033 …ne mmSDMA0_DEC_START_BASE_IDX 034 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f35 …ne mmSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 036 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010[all …]
27 // base address: 0x4828 …VGA_MEM_WRITE_PAGE_ADDR 0x000029 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 030 …VGA_MEM_READ_PAGE_ADDR 0x000131 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 035 // base address: 0x3b436 …CRTC8_IDX 0x002d38 …CRTC8_DATA 0x002d40 …GENFC_WT 0x002e42 …GENS1 0x002e[all …]
7 // base address: 0x08 …VGA_MEM_WRITE_PAGE_ADDR 0x00009 …VGA_MEM_WRITE_PAGE_ADDR 0x000010 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 011 …VGA_MEM_READ_PAGE_ADDR 0x000112 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 013 …VGA_RENDER_CONTROL 0x000015 …VGA_SEQUENCER_RESET_CONTROL 0x000117 …VGA_MODE_CONTROL 0x000219 …VGA_SURFACE_PITCH_SELECT 0x0003[all …]
27 // base address: 0x028 …VGA_MEM_WRITE_PAGE_ADDR 0x000029 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 030 …VGA_MEM_READ_PAGE_ADDR 0x000131 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 032 …VGA_RENDER_CONTROL 0x000034 …VGA_SEQUENCER_RESET_CONTROL 0x000136 …VGA_MODE_CONTROL 0x000238 …VGA_SURFACE_PITCH_SELECT 0x000340 …VGA_MEMORY_BASE_ADDRESS 0x0004[all …]
27 // base address: 0x4828 …dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x001229 …ne mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 033 // base address: 0x4c34 …dispdec_VGA_MEM_READ_PAGE_ADDR 0x001435 …ne mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 039 // base address: 0x040 …DC_PERFMON0_PERFCOUNTER_CNTL 0x002042 …DC_PERFMON0_PERFCOUNTER_CNTL2 0x002144 …DC_PERFMON0_PERFCOUNTER_STATE 0x0022[all …]
