Lines Matching +full:0 +full:x1294
15 #define ID_REV (0x00)
16 #define ID_REV_ID_MASK_ (0xFFFF0000)
17 #define ID_REV_ID_LAN7430_ (0x74300000)
18 #define ID_REV_ID_LAN7431_ (0x74310000)
20 (((id_rev) & 0xFFF00000) == 0x74300000)
21 #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF)
22 #define ID_REV_CHIP_REV_A0_ (0x00000000)
23 #define ID_REV_CHIP_REV_B0_ (0x00000010)
25 #define FPGA_REV (0x04)
26 #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF)
27 #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF)
29 #define HW_CFG (0x010)
30 #define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0)
34 #define PMT_CTL (0x014)
46 #define PMT_CTL_WUPS_MASK_ (0x00000003)
48 #define DP_SEL (0x024)
50 #define DP_SEL_MASK_ (0x0000001F)
51 #define DP_SEL_RFE_RAM (0x00000001)
56 #define DP_CMD (0x028)
57 #define DP_CMD_WRITE_ (0x00000001)
59 #define DP_ADDR (0x02C)
61 #define DP_DATA_0 (0x030)
63 #define E2P_CMD (0x040)
65 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)
66 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)
67 #define E2P_CMD_EPC_CMD_READ_ (0x00000000)
69 #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF)
71 #define E2P_DATA (0x044)
73 #define GPIO_CFG0 (0x050)
75 #define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit))
77 #define GPIO_CFG1 (0x054)
79 #define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit))
81 #define GPIO_CFG2 (0x058)
82 #define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit))
84 #define GPIO_CFG3 (0x05C)
86 #define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit))
88 #define FCT_RX_CTL (0xAC)
93 #define FCT_TX_CTL (0xC4)
98 #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2))
99 #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00)
103 #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F)
105 ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_)
107 #define MAC_CR (0x100)
116 #define MAC_CR_RST_ BIT(0)
118 #define MAC_RX (0x104)
120 #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000)
122 #define MAC_RX_RXEN_ BIT(0)
124 #define MAC_TX (0x108)
126 #define MAC_TX_TXEN_ BIT(0)
128 #define MAC_FLOW (0x10C)
131 #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF)
133 #define MAC_RX_ADDRH (0x118)
135 #define MAC_RX_ADDRL (0x11C)
137 #define MAC_MII_ACC (0x120)
139 #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800)
141 #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0)
142 #define MAC_MII_ACC_MII_READ_ (0x00000000)
143 #define MAC_MII_ACC_MII_WRITE_ (0x00000002)
144 #define MAC_MII_ACC_MII_BUSY_ BIT(0)
146 #define MAC_MII_DATA (0x124)
148 #define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130)
150 #define MAC_WUCSR (0x140)
155 #define MAC_WUCSR_BCST_EN_ BIT(0)
157 #define MAC_WK_SRC (0x144)
159 #define MAC_WUF_CFG0 (0x150)
164 #define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000)
165 #define MAC_WUF_CFG_TYPE_ALL_ (0x01000000)
167 #define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF)
169 #define MAC_WUF_MASK0_0 (0x200)
170 #define MAC_WUF_MASK0_1 (0x204)
171 #define MAC_WUF_MASK0_2 (0x208)
172 #define MAC_WUF_MASK0_3 (0x20C)
177 #define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index)))
178 #define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index)))
179 #define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index)))
180 #define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index)))
182 /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */
183 #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x)))
186 /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */
187 #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x)))
189 #define RFE_CTL (0x508)
196 #define RFE_RSS_CFG (0x554)
206 #define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0)
209 #define RFE_RSS_CFG_RSS_ENABLE_ BIT(0)
211 #define RFE_HASH_KEY(index) (0x558 + (index << 2))
213 #define RFE_INDX(index) (0x580 + (index << 2))
215 #define MAC_WUCSR2 (0x600)
217 #define INT_STS (0x780)
219 #define INT_BIT_ALL_RX_ (0x0F000000)
221 #define INT_BIT_ALL_TX_ (0x000F0000)
225 #define INT_BIT_MAS_ BIT(0)
227 #define INT_SET (0x784)
229 #define INT_EN_SET (0x788)
231 #define INT_EN_CLR (0x78C)
233 #define INT_STS_R2C (0x790)
235 #define INT_VEC_EN_SET (0x794)
236 #define INT_VEC_EN_CLR (0x798)
237 #define INT_VEC_EN_AUTO_CLR (0x79C)
238 #define INT_VEC_EN_(vector_index) BIT(0 + vector_index)
240 #define INT_VEC_MAP0 (0x7A0)
244 #define INT_VEC_MAP1 (0x7A4)
248 #define INT_VEC_MAP2 (0x7A8)
250 #define INT_MOD_MAP0 (0x7B0)
252 #define INT_MOD_MAP1 (0x7B4)
254 #define INT_MOD_MAP2 (0x7B8)
256 #define INT_MOD_CFG0 (0x7C0)
257 #define INT_MOD_CFG1 (0x7C4)
258 #define INT_MOD_CFG2 (0x7C8)
259 #define INT_MOD_CFG3 (0x7CC)
260 #define INT_MOD_CFG4 (0x7D0)
261 #define INT_MOD_CFG5 (0x7D4)
262 #define INT_MOD_CFG6 (0x7D8)
263 #define INT_MOD_CFG7 (0x7DC)
265 #define PTP_CMD_CTL (0x0A00)
272 #define PTP_CMD_CTL_PTP_RESET_ BIT(0)
273 #define PTP_GENERAL_CONFIG (0x0A04)
275 (0x7 << (1 + ((channel) << 2)))
276 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0)
283 (((value) & 0x7) << (1 + ((channel) << 2)))
286 #define PTP_INT_STS (0x0A08)
287 #define PTP_INT_EN_SET (0x0A0C)
288 #define PTP_INT_EN_CLR (0x0A10)
292 #define PTP_INT_BIT_TIMER_A_ BIT(0)
294 #define PTP_CLOCK_SEC (0x0A14)
295 #define PTP_CLOCK_NS (0x0A18)
296 #define PTP_CLOCK_SUBNS (0x0A1C)
297 #define PTP_CLOCK_RATE_ADJ (0x0A20)
299 #define PTP_CLOCK_STEP_ADJ (0x0A2C)
301 #define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF)
302 #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4))
303 #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4))
304 #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4))
305 #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4))
306 #define PTP_LATENCY (0x0A5C)
309 (((u32)(rx_latency)) & 0x0000FFFF)
310 #define PTP_CAP_INFO (0x0A60)
311 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4)
313 #define PTP_TX_MOD (0x0AA4)
314 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000)
316 #define PTP_TX_MOD2 (0x0AA8)
317 #define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001)
319 #define PTP_TX_EGRESS_SEC (0x0AAC)
320 #define PTP_TX_EGRESS_NS (0x0AB0)
321 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000)
322 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000)
323 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000)
324 #define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF)
326 #define PTP_TX_MSG_HEADER (0x0AB4)
327 #define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000)
328 #define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000)
330 #define DMAC_CFG (0xC00)
332 #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000)
333 #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070)
336 #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000)
337 #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001)
339 #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003)
341 #define DMAC_COAL_CFG (0xC04)
342 #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000)
349 #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00)
352 #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF)
356 #define DMAC_OBFF_CFG (0xC08)
357 #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00)
360 #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF)
364 #define DMAC_CMD (0xC0C)
371 #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel))
373 #define DMAC_INT_STS (0xC10)
374 #define DMAC_INT_EN_SET (0xC14)
375 #define DMAC_INT_EN_CLR (0xC18)
377 #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel))
379 #define RX_CFG_A(channel) (0xC40 + ((channel) << 6))
381 #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000)
384 #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000)
387 #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00)
392 #define RX_CFG_B(channel) (0xC44 + ((channel) << 6))
394 #define RX_CFG_B_RX_PAD_MASK_ (0x03000000)
395 #define RX_CFG_B_RX_PAD_0_ (0x00000000)
396 #define RX_CFG_B_RX_PAD_2_ (0x02000000)
397 #define RX_CFG_B_RDMABL_512_ (0x00040000)
398 #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF)
400 #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6))
402 #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6))
404 #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6))
406 #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6))
408 #define RX_HEAD(channel) (0xC58 + ((channel) << 6))
410 #define RX_TAIL(channel) (0xC5C + ((channel) << 6))
414 #define RX_CFG_C(channel) (0xC64 + ((channel) << 6))
418 #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007)
420 #define TX_CFG_A(channel) (0xD40 + ((channel) << 6))
422 #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000)
423 #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000)
426 #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00)
430 #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F)
434 #define TX_CFG_B(channel) (0xD44 + ((channel) << 6))
435 #define TX_CFG_B_TDMABL_512_ (0x00040000)
436 #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF)
438 #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6))
440 #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6))
442 #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6))
444 #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6))
446 #define TX_HEAD(channel) (0xD58 + ((channel) << 6))
448 #define TX_TAIL(channel) (0xD5C + ((channel) << 6))
453 #define TX_CFG_C(channel) (0xD64 + ((channel) << 6))
458 #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007)
460 #define OTP_PWR_DN (0x1000)
461 #define OTP_PWR_DN_PWRDN_N_ BIT(0)
463 #define OTP_ADDR_HIGH (0x1004)
464 #define OTP_ADDR_LOW (0x1008)
466 #define OTP_PRGM_DATA (0x1010)
468 #define OTP_PRGM_MODE (0x1014)
469 #define OTP_PRGM_MODE_BYTE_ BIT(0)
471 #define OTP_READ_DATA (0x1018)
473 #define OTP_FUNC_CMD (0x1020)
474 #define OTP_FUNC_CMD_READ_ BIT(0)
476 #define OTP_TST_CMD (0x1024)
479 #define OTP_CMD_GO (0x1028)
480 #define OTP_CMD_GO_GO_ BIT(0)
482 #define OTP_STATUS (0x1030)
483 #define OTP_STATUS_BUSY_ BIT(0)
486 #define STAT_RX_FCS_ERRORS (0x1200)
487 #define STAT_RX_ALIGNMENT_ERRORS (0x1204)
488 #define STAT_RX_FRAGMENT_ERRORS (0x1208)
489 #define STAT_RX_JABBER_ERRORS (0x120C)
490 #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210)
491 #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214)
492 #define STAT_RX_DROPPED_FRAMES (0x1218)
493 #define STAT_RX_UNICAST_BYTE_COUNT (0x121C)
494 #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220)
495 #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224)
496 #define STAT_RX_UNICAST_FRAMES (0x1228)
497 #define STAT_RX_BROADCAST_FRAMES (0x122C)
498 #define STAT_RX_MULTICAST_FRAMES (0x1230)
499 #define STAT_RX_PAUSE_FRAMES (0x1234)
500 #define STAT_RX_64_BYTE_FRAMES (0x1238)
501 #define STAT_RX_65_127_BYTE_FRAMES (0x123C)
502 #define STAT_RX_128_255_BYTE_FRAMES (0x1240)
503 #define STAT_RX_256_511_BYTES_FRAMES (0x1244)
504 #define STAT_RX_512_1023_BYTE_FRAMES (0x1248)
505 #define STAT_RX_1024_1518_BYTE_FRAMES (0x124C)
506 #define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250)
507 #define STAT_RX_TOTAL_FRAMES (0x1254)
508 #define STAT_EEE_RX_LPI_TRANSITIONS (0x1258)
509 #define STAT_EEE_RX_LPI_TIME (0x125C)
510 #define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C)
512 #define STAT_TX_FCS_ERRORS (0x1280)
513 #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284)
514 #define STAT_TX_CARRIER_ERRORS (0x1288)
515 #define STAT_TX_BAD_BYTE_COUNT (0x128C)
516 #define STAT_TX_SINGLE_COLLISIONS (0x1290)
517 #define STAT_TX_MULTIPLE_COLLISIONS (0x1294)
518 #define STAT_TX_EXCESSIVE_COLLISION (0x1298)
519 #define STAT_TX_LATE_COLLISIONS (0x129C)
520 #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0)
521 #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4)
522 #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8)
523 #define STAT_TX_UNICAST_FRAMES (0x12AC)
524 #define STAT_TX_BROADCAST_FRAMES (0x12B0)
525 #define STAT_TX_MULTICAST_FRAMES (0x12B4)
526 #define STAT_TX_PAUSE_FRAMES (0x12B8)
527 #define STAT_TX_64_BYTE_FRAMES (0x12BC)
528 #define STAT_TX_65_127_BYTE_FRAMES (0x12C0)
529 #define STAT_TX_128_255_BYTE_FRAMES (0x12C4)
530 #define STAT_TX_256_511_BYTES_FRAMES (0x12C8)
531 #define STAT_TX_512_1023_BYTE_FRAMES (0x12CC)
532 #define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0)
533 #define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4)
534 #define STAT_TX_TOTAL_FRAMES (0x12D8)
535 #define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC)
536 #define STAT_EEE_TX_LPI_TIME (0x12E0)
537 #define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC)
559 #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430)
560 #define PCI_DEVICE_ID_SMSC_LAN7431 (0x7431)
562 #define PCI_CONFIG_LENGTH (0x1000)
565 #define CSR_LENGTH (0x2000)
567 #define LAN743X_CSR_FLAG_IS_A0 BIT(0)
581 #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0)
634 #define GPIO_QUEUE_STARTED (0)
639 #define TX_FRAME_FLAG_IN_PROGRESS BIT(0)
641 #define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0)
724 #define LAN743X_ADAPTER_FLAG_OTP BIT(0)
730 #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index)
735 #define MAC_MII_WRITE 0
737 #define PHY_FLAG_OPENED BIT(0)
741 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF))
743 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0))
745 #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF))
753 (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0))
754 #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0)
755 #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0)
757 #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1)
760 #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000)
761 #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000)
762 #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000)
763 #define TX_DESC_DATA0_FS_ (0x20000000)
764 #define TX_DESC_DATA0_LS_ (0x10000000)
765 #define TX_DESC_DATA0_EXT_ (0x08000000)
766 #define TX_DESC_DATA0_IOC_ (0x04000000)
767 #define TX_DESC_DATA0_ICE_ (0x00400000)
768 #define TX_DESC_DATA0_IPE_ (0x00200000)
769 #define TX_DESC_DATA0_TPE_ (0x00100000)
770 #define TX_DESC_DATA0_FCS_ (0x00020000)
771 #define TX_DESC_DATA0_TSE_ (0x00010000)
772 #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF)
773 #define TX_DESC_DATA0_EXT_LSO_ (0x00200000)
774 #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF)
775 #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000)
784 #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
798 #define RX_DESC_DATA0_OWN_ (0x00008000)
800 #define RX_DESC_DATA0_FS_ (0x80000000)
801 #define RX_DESC_DATA0_LS_ (0x40000000)
802 #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000)
805 #define RX_DESC_DATA0_EXT_ (0x00004000)
806 #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF)
807 #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF)
809 #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2))
810 #error NET_IP_ALIGN must be 0 or 2
822 #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
833 #define RX_PROCESS_RESULT_NOTHING_TO_DO (0)