Home
last modified time | relevance | path

Searched +full:0 +full:x128 (Results 1 – 25 of 324) sorted by relevance

12345678910>>...13

/Linux-v6.1/drivers/clk/visconti/
Dclkc-tmpv770x.c35 { TMPV770X_CLK_PIPLL1_DIV4, "pipll1_div4", "pipll1", 0, 1, 4, },
37 { TMPV770X_CLK_PIPLL1_DIV2, "pipll1_div2", "pipll1", 0, 1, 2, },
39 { TMPV770X_CLK_PIPLL1_DIV1, "pipll1_div1", "pipll1", 0, 1, 1, },
42 { TMPV770X_CLK_PIDNNPLL_DIV1, "pidnnpll_div1", "pidnnpll", 0, 1, 1, },
43 { TMPV770X_CLK_PIREFCLK, "pirefclk", "osc2-clk", 0, 1, 1, },
44 { TMPV770X_CLK_WDTCLK, "wdtclk", "osc2-clk", 0, 1, 1, },
51 CLK_SET_RATE_PARENT, 0x34, 0x134, 4, 200,
55 CLK_SET_RATE_PARENT, 0x34, 0x134, 5, 20,
59 CLK_SET_RATE_PARENT, 0x34, 0x134, 6, 10,
63 CLK_SET_RATE_PARENT, 0x34, 0x134, 7, 4,
[all …]
/Linux-v6.1/drivers/clk/renesas/
Dr8a774a1-cpg-mssr.c78 DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
99 DEF_GEN3_SDH("sd0h", R8A774A1_CLK_SD0H, CLK_SDSRC, 0x074),
100 DEF_GEN3_SDH("sd1h", R8A774A1_CLK_SD1H, CLK_SDSRC, 0x078),
101 DEF_GEN3_SDH("sd2h", R8A774A1_CLK_SD2H, CLK_SDSRC, 0x268),
102 DEF_GEN3_SDH("sd3h", R8A774A1_CLK_SD3H, CLK_SDSRC, 0x26c),
103 DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, R8A774A1_CLK_SD0H, 0x074),
104 DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, R8A774A1_CLK_SD1H, 0x078),
105 DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268),
106 DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c),
115 DEF_DIV6P1("canfd", R8A774A1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
[all …]
Dr8a774b1-cpg-mssr.c96 DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074),
97 DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078),
98 DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268),
99 DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c),
100 DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074),
101 DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078),
102 DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268),
103 DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c),
112 DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
113 DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
[all …]
Dr8a774e1-cpg-mssr.c78 DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
99 DEF_GEN3_SDH("sd0h", R8A774E1_CLK_SD0H, CLK_SDSRC, 0x074),
100 DEF_GEN3_SDH("sd1h", R8A774E1_CLK_SD1H, CLK_SDSRC, 0x078),
101 DEF_GEN3_SDH("sd2h", R8A774E1_CLK_SD2H, CLK_SDSRC, 0x268),
102 DEF_GEN3_SDH("sd3h", R8A774E1_CLK_SD3H, CLK_SDSRC, 0x26c),
103 DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, R8A774E1_CLK_SD0H, 0x074),
104 DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, R8A774E1_CLK_SD1H, 0x078),
105 DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268),
106 DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c),
116 DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
[all …]
Dr8a7796-cpg-mssr.c83 DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
105 DEF_GEN3_SDH("sd0h", R8A7796_CLK_SD0H, CLK_SDSRC, 0x074),
106 DEF_GEN3_SDH("sd1h", R8A7796_CLK_SD1H, CLK_SDSRC, 0x078),
107 DEF_GEN3_SDH("sd2h", R8A7796_CLK_SD2H, CLK_SDSRC, 0x268),
108 DEF_GEN3_SDH("sd3h", R8A7796_CLK_SD3H, CLK_SDSRC, 0x26c),
109 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, R8A7796_CLK_SD0H, 0x074),
110 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, R8A7796_CLK_SD1H, 0x078),
111 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268),
112 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c),
122 DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
[all …]
Dr8a77965-cpg-mssr.c100 DEF_GEN3_SDH("sd0h", R8A77965_CLK_SD0H, CLK_SDSRC, 0x074),
101 DEF_GEN3_SDH("sd1h", R8A77965_CLK_SD1H, CLK_SDSRC, 0x078),
102 DEF_GEN3_SDH("sd2h", R8A77965_CLK_SD2H, CLK_SDSRC, 0x268),
103 DEF_GEN3_SDH("sd3h", R8A77965_CLK_SD3H, CLK_SDSRC, 0x26c),
104 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, R8A77965_CLK_SD0H, 0x074),
105 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, R8A77965_CLK_SD1H, 0x078),
106 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268),
107 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c),
117 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
118 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
[all …]
Dr8a7795-cpg-mssr.c81 DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
103 DEF_GEN3_SDH("sd0h", R8A7795_CLK_SD0H, CLK_SDSRC, 0x074),
104 DEF_GEN3_SDH("sd1h", R8A7795_CLK_SD1H, CLK_SDSRC, 0x078),
105 DEF_GEN3_SDH("sd2h", R8A7795_CLK_SD2H, CLK_SDSRC, 0x268),
106 DEF_GEN3_SDH("sd3h", R8A7795_CLK_SD3H, CLK_SDSRC, 0x26c),
107 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, R8A7795_CLK_SD0H, 0x074),
108 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, R8A7795_CLK_SD1H, 0x078),
109 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268),
110 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c),
120 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
[all …]
Dr8a779a0-cpg-mssr.c73 DEF_PLL(".pll20", CLK_PLL20, 0x0834),
74 DEF_PLL(".pll21", CLK_PLL21, 0x0838),
75 DEF_PLL(".pll30", CLK_PLL30, 0x083c),
76 DEF_PLL(".pll31", CLK_PLL31, 0x0840),
94 DEF_GEN4_Z("z0", R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0),
119 DEF_GEN4_SDH("sdh0", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870),
120 DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870),
126 DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
127 DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
128 DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/display/
Dsitronix,st7735r.yaml24 Adafruit 1.8" 160x128 Color TFT LCD (Product ID 358 or 618)
30 Okaya 1.44" 128x128 Color TFT LCD (E.g. Renesas YRSK-LCD-PMOD)
64 #size-cells = <0>;
66 display@0{
68 reg = <0>;
/Linux-v6.1/drivers/media/pci/cx18/
Dcx18-av-audio.c60 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
61 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq()
63 cx18_av_write4(cx, 0x108, 0x200d040f); in set_audclk_freq()
65 /* VID_PLL Fraction = 0x2be2fe */ in set_audclk_freq()
66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
67 cx18_av_write4(cx, 0x10c, 0x002be2fe); in set_audclk_freq()
69 /* AUX_PLL Fraction = 0x176740c */ in set_audclk_freq()
70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
71 cx18_av_write4(cx, 0x110, 0x0176740c); in set_audclk_freq()
74 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq()
[all …]
/Linux-v6.1/drivers/phy/qualcomm/
Dphy-qcom-qmp-pcie-qhp.h10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
[all …]
Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-qserdes-pll.h10 #define QSERDES_PLL_BG_TIMER 0x00c
11 #define QSERDES_PLL_SSC_PER1 0x01c
12 #define QSERDES_PLL_SSC_PER2 0x020
13 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
14 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
15 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
16 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
17 #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
18 #define QSERDES_PLL_CLK_ENABLE1 0x040
19 #define QSERDES_PLL_SYS_CLK_CTRL 0x044
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dqcom,qmp-usb3-dp-phy.yaml83 "^usb3-phy@[0-9a-f]+$":
113 const: 0
116 const: 0
124 "^dp-phy@[0-9a-f]+$":
143 const: 0
181 reg = <0x088e9000 0x18c>,
182 <0x088e8000 0x10>,
183 <0x088ea000 0x40>;
187 ranges = <0x0 0x088e9000 0x2000>;
203 reg = <0x200 0x128>,
[all …]
Dberlin-usb-phy.txt6 - #phys-cells: should be 0
13 reg = <0xf774000 0x128>;
14 #phy-cells = <0>;
15 resets = <&chip 0x104 14>;
/Linux-v6.1/drivers/clk/mediatek/
Dclk-mt7622.c296 .set_ofs = 0x8,
297 .clr_ofs = 0x8,
298 .sta_ofs = 0x8,
302 .set_ofs = 0x40,
303 .clr_ofs = 0x44,
304 .sta_ofs = 0x48,
308 .set_ofs = 0x120,
309 .clr_ofs = 0x120,
310 .sta_ofs = 0x120,
314 .set_ofs = 0x128,
[all …]
Dclk-mt6795-topckgen.c17 * So we model these clocks' rate as 0, to denote it's not an actual rate.
19 #define DUMMY_RATE 0
23 (_reg + 0x4), (_reg + 0x8), _shift, _width, \
24 _gate, 0, -1, _flags)
453 0x40, 0, 3, 7, CLK_IS_CRITICAL),
455 0x40, 8, 1, 15, CLK_IS_CRITICAL),
457 0x40, 16, 1, 23, CLK_IS_CRITICAL),
458 TOP_MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x40, 24, 3, 31, 0),
460 TOP_MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x50, 0, 2, 7, 0),
461 TOP_MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x50, 8, 4, 15, 0),
[all …]
/Linux-v6.1/arch/x86/crypto/
Dcrc32-pclmul_asm.S7 * CRC32 polynomial:0x04c11db7(BE)/0xEDB88320(LE)
24 * [x4*128+32 mod P(x) << 32)]' << 1 = 0x154442bd4
25 * #define CONSTANT_R1 0x154442bd4LL
27 * [(x4*128-32 mod P(x) << 32)]' << 1 = 0x1c6e41596
28 * #define CONSTANT_R2 0x1c6e41596LL
31 .octa 0x00000001c6e415960000000154442bd4
33 * [(x128+32 mod P(x) << 32)]' << 1 = 0x1751997d0
34 * #define CONSTANT_R3 0x1751997d0LL
36 * [(x128-32 mod P(x) << 32)]' << 1 = 0x0ccaa009e
37 * #define CONSTANT_R4 0x0ccaa009eLL
[all …]
/Linux-v6.1/drivers/clk/imx/
Dclk-imx8mn.c334 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mn_clocks_probe()
343 base = of_iomap(np, 0); in imx8mn_clocks_probe()
350 …hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mn_clocks_probe()
351 …hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
352 …hws[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
353 …hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mn_clocks_probe()
354 …hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
355 …hws[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
356 …hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
357 …hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mn_clocks_probe()
[all …]
/Linux-v6.1/drivers/tty/serial/8250/
D8250_boca.c13 SERIAL8250_PORT(0x100, 12),
14 SERIAL8250_PORT(0x108, 12),
15 SERIAL8250_PORT(0x110, 12),
16 SERIAL8250_PORT(0x118, 12),
17 SERIAL8250_PORT(0x120, 12),
18 SERIAL8250_PORT(0x128, 12),
19 SERIAL8250_PORT(0x130, 12),
20 SERIAL8250_PORT(0x138, 12),
21 SERIAL8250_PORT(0x140, 12),
22 SERIAL8250_PORT(0x148, 12),
[all …]
/Linux-v6.1/drivers/media/platform/mediatek/mdp3/
Dmdp_reg_rdma.h10 #define MDP_RDMA_EN 0x000
11 #define MDP_RDMA_RESET 0x008
12 #define MDP_RDMA_CON 0x020
13 #define MDP_RDMA_GMCIF_CON 0x028
14 #define MDP_RDMA_SRC_CON 0x030
15 #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
16 #define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x068
17 #define MDP_RDMA_MF_SRC_SIZE 0x070
18 #define MDP_RDMA_MF_CLIP_SIZE 0x078
19 #define MDP_RDMA_MF_OFFSET_1 0x080
[all …]
/Linux-v6.1/drivers/video/fbdev/
Dwm8505fb_regs.h15 * Color space select register, default value 0x1c
22 #define WMT_GOVR_COLORSPACE 0x1e4
28 #define WMT_GOVR_COLORSPACE1 0x30
30 #define WMT_GOVR_CONTRAST 0x1b8
31 #define WMT_GOVR_BRGHTNESS 0x1bc /* incompatible with RGB? */
34 #define WMT_GOVR_FBADDR 0x90
35 #define WMT_GOVR_FBADDR1 0x94 /* UV offset in YUV mode */
38 #define WMT_GOVR_XPAN 0xa4
39 #define WMT_GOVR_YPAN 0xa0
41 #define WMT_GOVR_XRES 0x98
[all …]
/Linux-v6.1/arch/s390/crypto/
Dcrc32be-vx.S39 * R3 = x128+64 mod P(x)
40 * R4 = x128 mod P(x)
51 * The righmost doubleword can be 0 to prevent contribution to the result or
57 * P(x) = 0x04C11DB7
58 * P'(x) = 0xEDB88320
62 .quad 0x08833794c, 0x0e6228b11 # R1, R2
63 .quad 0x0c5b9cd4c, 0x0e8a45605 # R3, R4
64 .quad 0x0f200aa66, 1 << 32 # R5, x32
65 .quad 0x0490d678d, 1 # R6, 1
66 .quad 0x104d101df, 0 # u
[all …]
/Linux-v6.1/arch/arm/mach-davinci/
Dclock.h13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]

12345678910>>...13