Lines Matching +full:0 +full:x128
73 DEF_PLL(".pll20", CLK_PLL20, 0x0834),
74 DEF_PLL(".pll21", CLK_PLL21, 0x0838),
75 DEF_PLL(".pll30", CLK_PLL30, 0x083c),
76 DEF_PLL(".pll31", CLK_PLL31, 0x0840),
94 DEF_GEN4_Z("z0", R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0),
119 DEF_GEN4_SDH("sdh0", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870),
120 DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870),
126 DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
127 DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
128 DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
129 DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 0x884),
248 * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16
249 * 0 1 20 x 1 x106 x180 x106 x120 x160 /19
250 * 1 0 Prohibited setting
251 * 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32
257 { 1, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 16, },
258 { 1, 106, 1, 0, 0, 0, 0, 120, 1, 160, 1, 0, 0, 19, },
259 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
260 { 2, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 32, },