Lines Matching +full:0 +full:x128
96 DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074),
97 DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078),
98 DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268),
99 DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c),
100 DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074),
101 DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078),
102 DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268),
103 DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c),
112 DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
113 DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
114 DEF_DIV6P1("mso", R8A774B1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
115 DEF_DIV6P1("hdmi", R8A774B1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
128 DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1),
259 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
260 * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16
261 * 0 0 1 0 Prohibited setting
262 * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16
263 * 0 1 0 0 20 x 1 x150 x160 x160 x120 /19
264 * 0 1 0 1 20 x 1 x150 x160 x106 x120 /19
265 * 0 1 1 0 Prohibited setting
266 * 0 1 1 1 20 x 1 x150 x160 x160 x120 /19
267 * 1 0 0 0 25 x 1 x120 x128 x128 x96 /24
268 * 1 0 0 1 25 x 1 x120 x128 x84 x96 /24
269 * 1 0 1 0 Prohibited setting
270 * 1 0 1 1 25 x 1 x120 x128 x128 x96 /24
271 * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32
272 * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32
273 * 1 1 1 0 Prohibited setting
285 { 0, /* Prohibited setting */ },
289 { 0, /* Prohibited setting */ },
293 { 0, /* Prohibited setting */ },
297 { 0, /* Prohibited setting */ },
313 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); in r8a774b1_cpg_mssr_init()